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74VHC86 Datasheet(PDF) 1 Page - Fairchild Semiconductor |
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74VHC86 Datasheet(HTML) 1 Page - Fairchild Semiconductor |
1 / 7 page © 2005 Fairchild Semiconductor Corporation DS011517 www.fairchildsemi.com November 1992 Revised February 2005 74VHC86 Quad 2-Input Exclusive-OR Gate General Description The VHC86 is an advanced high speed CMOS Quad Exclusive OR Gate fabricated with silicon gate CMOS tech- nology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply volt- age. This device can be used to interface 5V to 3V systems and on two supply systems such as battery back up. This circuit prevents device destruction due to mismatched sup- ply and input voltages. Features s High Speed: tPD 4.8 ns (typ) at VCC 5V s Low Power Dissipation: ICC 2 PA (Max.) @ TA 25qC s High Noise Immunity: VNIH VNIL 28% VCC (Min.) s Power down protection is provided on all inputs s Low Noise: VOLP 0.8V (Max.) s Pin and Function Compatible with 74HC86 Ordering Code: Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STS-020B). Device available in Tape and Reel only. Logic Symbol IEEE/IEC Pin Descriptions Connection Diagram Truth Table Order Number Package Package Description Number 74VHC86M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74VHC86SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHC86MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC86MTCX_NL (Note 1) MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC86N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Pin Names Description A0–A3 Inputs B0–B3 Inputs O0–O3 Outputs AB O LLL LH H HL H HH L |
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