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EPM3128ATC100-10N Datasheet(PDF) 7 Page - Altera Corporation |
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EPM3128ATC100-10N Datasheet(HTML) 7 Page - Altera Corporation |
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7 / 46 page  Altera Corporation 7 MAX 3000A Programmable Logic Device Family Data Sheet For registered functions, each macrocell flipflop can be individually programmed to implement D, T, JK, or SR operation with programmable clock control. The flipflop can be bypassed for combinatorial operation. During design entry, the designer specifies the desired flipflop type; the Altera development system software then selects the most efficient flipflop operation for each registered function to optimize resource utilization. Each programmable register can be clocked in three different modes: ■ Global clock signal mode, which achieves the fastest clock–to–output performance. ■ Global clock signal enabled by an active–high clock enable. A clock enable is generated by a product term. This mode provides an enable on each flipflop while still achieving the fast clock–to–output performance of the global clock. ■ Array clock implemented with a product term. In this mode, the flipflop can be clocked by signals from buried macrocells or I/O pins. Two global clock signals are available in MAX 3000A devices. As shown in Figure 1, these global clock signals can be the true or the complement of either of the two global clock pins, GCLK1 or GCLK2. Each register also supports asynchronous preset and clear functions. As shown in Figure 2, the product–term select matrix allocates product terms to control these operations. Although the product–term–driven preset and clear from the register are active high, active–low control can be obtained by inverting the signal within the logic array. In addition, each register clear function can be individually driven by the active–low dedicated global clear pin (GCLRn). All registers are cleared upon power-up. By default, all registered outputs drive low when the device is powered up. You can set the registered outputs to drive high upon power-up through the Quartus® II software. Quartus II software uses the NOT Gate Push-Back method, which uses an additional macrocell to set the output high. To set this in the Quartus II software, go to the Assignment Editor and set the Power-Up Level assignment for the register to High. |
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