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DM74ALS09N Datasheet(PDF) 1 Page - Fairchild Semiconductor |
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DM74ALS09N Datasheet(HTML) 1 Page - Fairchild Semiconductor |
1 / 4 page © 2000 Fairchild Semiconductor Corporation DS006179 www.fairchildsemi.com September 1986 Revised February 2000 DM74ALS09 Quad 2-Input AND Gate with Open Collector Outputs General Description This device contains four independent gates, each of which performs the logic AND function. The open-collector out- puts require external pull-up resistors for proper logical operation. Pull-Up Resistor Equations Where: N1 (IOH) = total maximum output HIGH current for all outputs tied to pull-up resistor N2 (IIH) = total maximum input HIGH current for all inputs tied to pull-up resistor N3 (IIL) = total maximum input LOW current for all inputs tied to pull-up resistor Features s Switching specifications at 50 pF s Switching specifications guaranteed over full tempera- ture and VCC range s Advanced oxide-isolated, ion-implanted Schottky TTL process s Functionally and pin for pin compatible with Schottky and low power Schottky TTL counterpart s Improved AC performance over Schottky and low power Schottky counterparts Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Y = AB H = HIGH Logic Level L = LOW Logic Level Order Number Package Number Package Description DM74ALS09M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74ALS09N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Inputs Output AB Y LL L LH L HL L HH H |
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