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AD9789BBC Datasheet(PDF) 5 Page - Analog Devices |
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AD9789BBC Datasheet(HTML) 5 Page - Analog Devices |
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5 / 76 page  AD9789 Rev. A | Page 5 of 76 DIGITAL SPECIFICATIONS AVDD33 = DVDD33 = 3.3 V, CVDD18 = DVDD18 = 1.8 V, DVDD15 = 1.5 V, fDAC = 2.4 GHz, IFS = 20 mA, LVDS drivers and receivers are compliant with the IEEE Std 1596.3-1996 reduced range link, unless otherwise noted. Table 2. Parameter Min Typ Max Unit CMOS DATA INPUTS (D[31:0], P0, P1) Input Voltage High, VIH 2.0 3.3 V Input Voltage Low, VIL 0 0.8 V Input Current High, IIH −10 +10 μA Input Current Low, IIL −10 +10 μA Input Capacitance 2 pF Setup Time, CMOS Data Input to CMOS_DCO1 5.3 ns Hold Time, CMOS Data Input to CMOS_DCO1 −1.4 ns CMOS OUTPUTS (CMOS_FS, CMOS_DCO) Output Voltage High, VOH 2.4 3.3 V Output Voltage Low, VOL 0 0.4 V Output Current High, IOH 12 mA Output Current Low, IOL 12 mA Maximum Clock Rate (CMOS_DCO) 150 MHz CMOS_DCO to CMOS_FS Delay 0.28 0.85 ns LVDS DATA INPUTS (D[15:0]P, D[15:0]N, PARP, PARN) Input Voltage Range, VIA or VIB 825 1575 mV Input Differential Threshold, VIDTH −100 +100 mV Input Differential Hysteresis, VIDTHH, VIDTHL 25 mV Input Differential Input Impedance, RIN 80 120 Ω Maximum LVDS Input Rate 150 MSPS Setup Time, LVDS Differential Input Data to Differential DCOx2 1.41 ns Hold Time, LVDS Differential Input Data to Differential DCOx2 0.24 ns LVDS OUTPUTS (DCOP, DCON, FSP, FSN) DCOP, FSP = VOA; DCON, FSN = VOB; 100 Ω Termination Output Voltage High, VOA or VOB 1375 mV Output Voltage Low, VOA or VOB 1025 mV Output Differential Voltage, |VOD| 150 200 250 mV Output Offset Voltage, VOS 1150 1250 mV Output Impedance, Single Ended, RO 40 140 Ω RO Mismatch Between A and B, ∆RO 10 % Change in |VOD| Between 0 and 1, |∆VOD| 25 mV Change in VOS Between 0 and 1, ∆VOS 25 mV Output Current—Driver Shorted to Ground, ISA, ISB 20 mA Output Current—Drivers Shorted Together, ISAB 4 mA Power-Off Output Leakage, |IXA|, |IXB| 10 mA Maximum Clock Rate (DCOP, DCON) 150 MHz DCOx to FSx Delay 0.12 0.37 ns DAC CLOCK INPUT (CLKP, CLKN)3 Differential Peak Voltage 1.4 1.8 V Common-Mode Voltage 900 mV DAC Clock Rate 2400 MHz SERIAL PERIPHERAL INTERFACE Maximum Clock Rate (fSCLK, 1/tSCLK) 25 MHz Minimum Pulse Width High, tPWH 20 ns Minimum Pulse Width Low, tPWL 20 ns Minimum SDIO and CS to SCLK Setup, tDS 10 ns |
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