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DM74ALS165M Datasheet(PDF) 1 Page - Fairchild Semiconductor |
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DM74ALS165M Datasheet(HTML) 1 Page - Fairchild Semiconductor |
1 / 6 page © 2000 Fairchild Semiconductor Corporation DS006712 www.fairchildsemi.com January 1986 Revised February 2000 DM74ALS165 8-Bit Parallel In/Serial Out Shift Register General Description The DM74ALS165 is an 8-bit serial register that, when clocked, shifts the data toward serial output, QH. Parallel-in access to each stage is provided by eight individual direct data inputs that are enabled by a low level at the SH/LD input. The DM74ALS165 also features a clock inhibit func- tion and a complemented serial output, QH. Clocking is accomplished by a LOW-to-HIGH transition of the CLK input while SH/LD is held HIGH and CLK INH is held LOW. The functions of the CLK and CLK INH (clock inhibit) inputs are interchangeable. Since a LOW CLK input and a LOW-to-HIGH transition of CLK INH will also accom- plish clocking, CLK INH should be changed to the high level only while the CLK input is HIGH. Parallel loading is inhibited when SH/LD is held HIGH. The parallel inputs to the register are enabled while SH/LD is LOW indepen- dently of the levels of CLK, CLK INH, or SER inputs. Features s Complementary outputs s Direct overriding load (data) inputs s Gated clock inputs s Parallel-to-serial data conversion Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table H = HIGH Level (steady-state), L = LOW Level (steady-state) X = Don't Care (any input, including transitions) ↑ = Transition from LOW-to-HIGH level a...h = The level of steady-state input at inputs A through H, respectively QA0, QB0, QH0 = The level of QA, QB, or QH, respectively, before the indicated steady-state input conditions were established QAn, QGn = The level of QA or QG, respectively, before the most recent ↑ transition of the clock Order Number Package Number Package Description DM74ALS165M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74ALS165N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Inputs Internal Shift/ Clock Clock Serial Parallel Outputs Output Load Inhibit A...H QA QB QH L X X X a...h a b h HL L X X QA0 QB0 QH0 HL ↑ HX H QAn QGn HL ↑ LX L QAn QGn H ↑ LH X H QAn QGn H ↑ LL X L QAn QGn HH X X X QA0 QB0 QH0 |
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