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ISLA214P25 Datasheet(PDF) 13 Page - Intersil Corporation |
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ISLA214P25 Datasheet(HTML) 13 Page - Intersil Corporation |
13 / 25 page Application Note 1837 13 AN1837.0 May 3, 2013 Tested Performance Over ADC Input VCM Setting Using the available ADC common mode voltage servo loop feature, it is an easy matter to move the DC operating voltage at the ADC inputs around and verify the range of good performance. Using the same basic targets of -2dBFs with a fixed Fin at 30MHz, one test board was swept from 0.9VCM to 1.1VCM. The figure of merit here was the THD as the various spurious are moving around a lot with VCM but the overall THD is relatively constant. Figure 20 shows this test at two clock frequencies. The 500MSPS data is relatively insensitive to VCM input over this range showing very robust performance to varying VCM input voltages. Overall improved spurious performance has been observed with this ADC at lower clock rates and the 450MSPS data shows a bit more sensitivity to the ADC input VCM setting. In this test, the DC operating points through the FDA are not changing, none of the response shapes are changing up to the ADC, the only variable is the DC average input voltage for the signal being delivered to the ADC input pins. This is exercising fine scale input impedance nonlinearities in the ADC against the source impedance of the filter. While very robust over a relatively wide input VCM range, the plot above suggested a 0.96VCM set point for this board and that is the delivered condition. Changing the filter design and/or ADC might suggest a reset on that target ADC VCM voltage. This is easily accomplished using the VCM servo loop feature. Tested Performance with Fixed FIN and Narrow Clock Range Around 500MSPS Since it seemed the FFT improved somewhat in dropping just below 500MSPS, a ±50MSPS range around 500MSPS was evaluated with a fixed 50MHz input generating a -2dBFS in the FFT. Looking again at the THD since the various spurious are moving around a lot with each test, gives the example performance of Figure 21. This is indeed showing a pretty rapid improvement in THD dropping below 500MSPS and a good guardband above 500MSPS for acceptable performance. While it is not suggested that the ADC be operated above 500MSPS, this plot does show a good margin above that before catastrophic falloff in the THD. This is intended to add over temperature margin in the ADC performance. 2-Tone, 3rd Order IM3 Testing Since the board passes frequencies to 100MHz, duplicating the 70MHz IM3 performance reported in the ISLA214P50 data sheet will show the combined performance for the ADC and the interface circuit. The plot from the ISLA214P50 data sheet (Figure 16 there) is shown in Figure 22. This is reporting a -88dBFS 3rd order intermodulation spurious for the 2 close in spurs at ±3ΔFIN around the midpoint – that would be at 69MHz and 71MHz here. Converting this dBFS to dBc gives -80dBc for the IM3. For this broadband test, the IM2 is also apparent at 141MHz and 1MHz. Duplicating this set up with slightly lower carriers (-8dBFS vs -7dBFS on the ADC data sheet) at 69.5MHz and 70.5Mz gives the wideband FFT of Figure 23. In this case, with 2 test tone inputs, the reported SNR does not compute correctly. It is easy to see here that the IM2 at 140MHz has been suppressed quite a lot by the combined excellent even order suppression in the interface circuit and the interstage filter. The other IM2 at 1MHz is also lower. Zooming in on a 65MHz to 75MHz range in Figure 24 shows exceptionally low 3rd order terms in this solution. FIGURE 20. THD vs ADC INPUT COMMON MODE VOLTAGE -89 -88 -87 -86 -85 -84 -83 0.90 0.95 1.00 1.05 1.10 1.15 1.20 VCM SETTING AT ADC INPUTS (V) 500MSPS 450MSPS FIGURE 21. THD vs FCLK AROUND THE 500MSPS SPECIFIED MAXIMUM CLOCK RATE FIGURE 22. ISLA214P50 IM3 PLOT AT 70MHz AND 71MHz INPUTS FREQUENCIES -88 -86 -84 -82 -80 -78 450 470 490 510 530 550 FCLK (MHz) THD 0 50 100 150 200 250 -120 -100 -80 -60 -40 -20 0 FREQUENCY (MHz) IMD2 IMD3 2ND HARMONICS 3RD HARMONICS IMD3 = -88dBFS |
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Similar Description - ISLA214P25 |
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