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ISLA214P25 Datasheet(PDF) 26 Page - Intersil Corporation |
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ISLA214P25 Datasheet(HTML) 26 Page - Intersil Corporation |
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26 / 39 page  ISLA214P50 26 FN7571.2 December 10, 2012 Bits 3:0 These bits should always mirror bits 4:7 to avoid ambiguity in bit ordering. ADDRESS 0X02: BURST_END If a series of sequential registers are to be set, burst mode can improve throughput by eliminating redundant addressing. Setting the burst_end address determines the end of the transfer; during a write operation, the user must be cautious to transmit the correct number of bytes based on the starting and ending addresses. Bits 7:0 Burst End Address This register value determines the ending address of the burst data. Device Information ADDRESS 0X08: CHIP_ID ADDRESS 0X09: CHIP_VERSION The generic die identifier and a revision number, respectively, can be read from these two registers. Device Configuration/Control A common SPI map, which can accommodate single-channel or multi-channel devices, is used for all Intersil A/D products. ADDRESS 0X20: OFFSET_COARSE_ADC0 ADDRESS 0X21: OFFSET_FINE_ADC0 The input offset of the A/D core can be adjusted in fine and coarse steps. Both adjustments are made via an 8-bit word as detailed in Table 5. The data format is twos complement. The default value of each register will be the result of the self-calibration after initial power-up. If a register is to be incremented or decremented, the user should first read the register value then write the incremented or decremented value back to the same register. Bit 0 in register 0xFE must be set high to enable updates written to 0x20 and 0x21 to be used by the ADC (see description for 0xFE). ADDRESS 0X22: GAIN_COARSE__ADC0 ADDRESS 0X23: GAIN_MEDIUM_ADC0 ADDRESS 0X24: GAIN_FINE_ADC0 Gain of the A/D core can be adjusted in coarse, medium and fine steps. Coarse gain is a 4-bit adjustment while medium and fine are 8-bit. Multiple Coarse Gain Bits can be set for a total adjustment range of ±4.2%. (‘0011’ ≅ -4.2% and ‘1100’ ≅ +4.2%) It is recommended to use one of the coarse gain settings (-4.2%, -2.8%, -1.4%, 0, 1.4%, 2.8%, 4.2%) and fine-tune the gain using the registers at 23h and 24h. The default value of each register will be the result of the self-calibration after initial power-up. If a register is to be incremented or decremented, the user should first read the register value then write the incremented or decremented value back to the same register. Bit 0 in register 0xFE must be set high to enable updates written to 0x26 and 0x27 to be used by the ADC (see description for 0xFE). ADDRESS 0X25: MODES Two distinct reduced power modes can be selected. By default, the tri-level NAPSLP pin can select normal operation, nap or sleep modes (refer to“Nap/Sleep” on page 21). This functionality can be overridden and controlled through the SPI. This is an indexed function when controlled from the SPI, but a global function when driven from the pin. This register is not changed by a Soft Reset. ADDRESS 0X26: OFFSET_COARSE_ADC1 ADDRESS 0X27: OFFSET_FINE_ADC1 The input offset of A/D core#1 can be adjusted in fine and coarse steps in the same way that offset for core#0 can be adjusted. Both adjustments are made via an 8-bit word as detailed in Table 5. The data format is twos complement. The default value of each register will be the result of the self- calibration after initial power-up. If a register is to be incremented or decremented, the user should first read the register value then write the incremented or decremented value back to the same register. TABLE 5. OFFSET ADJUSTMENTS PARAMETER 0x20[7:0] COARSE OFFSET 0x21[7:0] FINE OFFSET Steps 255 255 –Full Scale (0x00) -133LSB (-47mV) -5LSB (-1.75mV) Mid–Scale (0x80) 0.0LSB (0.0mV) 0.0LSB +Full Scale (0xFF) +133LSB (+47mV) +5LSB (+1.75mV) Nominal Step Size 1.04LSB (0.37mV) 0.04LSB (0.014mV) TABLE 6. COARSE GAIN ADJUSTMENT 0x22[3:0] core 0 0x26[3:0] core 1 NOMINAL COARSE GAIN ADJUST (%) Bit3 +2.8 Bit2 +1.4 Bit1 -2.8 Bit0 -1.4 TABLE 7. MEDIUM AND FINE GAIN ADJUSTMENTS PARAMETER 0x23[7:0] MEDIUM GAIN 0x24[7:0] FINE GAIN Steps 256 256 –Full Scale (0x00) -2% -0.20% Mid–Scale (0x80) 0.00% 0.00% +Full Scale (0xFF) +2% +0.2% Nominal Step Size 0.016% 0.0016% TABLE 8. POWER-DOWN CONTROL VALUE 0x25[2:0] POWER DOWN MODE 000 Pin Control 001 Normal Operation 010 Nap Mode 100 Sleep Mode |
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