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FAN5231 Datasheet(PDF) 11 Page - Fairchild Semiconductor

Part # FAN5231
Description  Precision Dual PWM Controller And Linear Regulator for Notebook CPUs
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Manufacturer  FAIRCHILD [Fairchild Semiconductor]
Direct Link  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

FAN5231 Datasheet(HTML) 11 Page - Fairchild Semiconductor

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FAN5231
REV. 1.1.1 8/15/01
11
The converter output voltage is applied to the negative input
of the hysteretic comparator. The voltage on the reference
input of the hysteretic comparator is the DAC output voltage
with a small addition of the clock frequency pulses. Syn-
chronization of the upper MOSFET turn-on pulses with the
main clock positively contributes to the seamless transition
between the operation modes.
Operation During Processor Mode Changes
The PWM1 controller is specially designed to provide “on
the fly” automatic core voltage changes required by some
advanced processors for mobile applications. Dual core volt-
age and operation frequency scaling allows for significant
power savings without sacrificing system performance in
battery operation mode.
As processor mode changes can happen when chip is in
PWM or hysteretic mode, measures were taken to provide
equally fast response to these changes. As soon as a DAC
code change is received, the chip is switched into the forced
PWM mode for about 150ms regardless of the load level.
Operating the controller in the synhronous PWM mode
allows faster output voltage transitions especially when a
downward output voltage change is commanded.
I/O Converter Architecture
The I/O converter architecture is close to the one of the core
converter. It has the same mode control logic and can operate
in a costant frequency PWM mode or in the hysteretic mode
depending on the load level, but its structure is much simpler
mainly because of absense of the differential input amlifier
and the DAC. This controller is synchronized to the same
clock as the core converter, but out-of phase. Those, some
reduction of the input current ripple is achieved.
Gate Control Logic
The gate control logic translates generated PWM signals
into the MOSFETs gate drive signals providing necessary
amplification, level shift and shoot-trough protection. Also,
it incorporates functions that help to optimize the IC
performance over a wide range of operating conditions.
As MOSFET switching time can very dramatically from
type to type and with input voltage variation, gate control
logic provides adaptive dead time by monitoring gate volt-
ages of both upper and lower MOSFETs.
Output Voltage Adjustment
The output voltage of the I/O converter can be increased by
as much as 10% by inserting a resistor divider in the feed-
back line.
Fault Protection
All three outputs are monitored and protected against
extreme overload, short circuit and under-voltage conditions.
Both PWM outputs are monitored and protected from over-
voltage conditions. Only monitoring functions for over-volt-
age conditions is incorporated for the linear regulator.
A sustained overload on any output latches-off all the con-
verters and sets the PGOOD pin low. The chip operation can
be restored by cycling VCC voltage or EN pin.
Figure 10. I/O Converter Load Transient in PWM Mode
Figure 11. I/O Converter Load Transient
with Mode Change
Over-Current Protection
Both PWM controllers use the lower MOSFET’s on-resis-
tance — rDS(ON) to monitor the current for protection against
shorted outputs. The sensed voltage drop after amplification
is compared with an internally set threshold. Several scenar-
ios of the current protection circuit behavior are possible.
If load step is strong enough to pull output voltage lower
than the under-voltage threshold, chip shuts down. If the out-
put voltage sag does not reach the under-voltage threshold
but the current exceeds the over-current threshold, the pulse
skipping circuit is activated. This breaks the output voltage
regulation and limits the current supplied to the load.
Because of the nature of used current sensing technique, and
to accommodate wide range of the rDS(ON) variation, the
value of the threshold should represent overload current
about 180% of the nominal value. This could lead to the situ-
ation where the converter continuously delivers power about
two times the nominal without significant drop in the output
Ch1 50mV
Ch2 500mA
M50µs
1
2
VIO
I IO
Ch1 50mV
Ch2 500mA
M50µs
1
2
VIO
I IO


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