W631GG6KB12I datasheet(7/158 Pages) WINBOND

Part #	W631GG6KB12I

Description	Double Data Rate architecture: two data transfers per clock cycle

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Manufacturer	WINBOND [Winbond]

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W631GG6KB

Publication Release Date: Feb. 27, 2013

Revision A04

- 7 -

4.

KEY PARAMETERS

Speed Bin

DDR3-1866

DDR3-1600

DDR3-1333

Unit

CL-nRCD-nRP

13-13-13

11-11-11

9-9-9

Part Number Extension

-11

-12/12I/12A/12K -15/15I/15A/15K

Parameter

Sym.

Min.

Max.

Min.

Max.

Min.

Max.

Maximum operating frequency using maximum

allowed settings for Sup_CL and Sup_CWL

fCKMAX



933



800



667

MHz

Internal read command to first data

tAA

13.91

20

13.75

(13.125)

7

20

13.5

(13.125)

7

20

nS

ACT to internal read or write delay time

tRCD

13.91



13.75

(13.125)

7



13.5

(13.125)

7



nS

PRE command period

tRP

13.91



13.75

(13.125)

7



13.5

(13.125)

7



nS

ACT to ACT or REF command period

tRC

47.91



48.75

(48.125)

7



49.5

(49.125)

7



nS

ACT to PRE command period

tRAS

34

9 * tREFI

35

9 * tREFI

36

9 * tREFI

nS

CL = 6

CWL = 5

tCK(AVG)

2.5

3.3

2.5

3.3

2.5

3.3

nS

CL = 7

CWL = 6

tCK(AVG)

Reserved

1.875

<2.5

1.875

<2.5

nS

CL = 8

CWL = 6

tCK(AVG)

1.875

<2.5

1.875

<2.5

1.875

<2.5

nS

CL = 9

CWL = 7

tCK(AVG)

Reserved

1.5

<1.875

1.5

<1.875

nS

CL = 10

CWL = 7

tCK(AVG)

1.5

<1.875

1.5

<1.875

1.5

<1.875

nS

CL = 11

CWL = 8

tCK(AVG)

Reserved

1.25

<1.5

Reserved

nS

CL = 13

CWL = 9

tCK(AVG)

1.07

<1.25

Reserved

nS

Supported CL Settings

Sup_CL

6, 8, 10, 13

6, (7), 8, (9), 10, 11

6, (7), 8, 9, 10

nCK

Supported CWL Settings

Sup_CWL

5, 6, 7, 9

5, 6, 7, 8

5, 6, 7

nCK

Average periodic

refresh Interval

-40°C

≤ TCASE ≤ 85°C

tREFI



*2



7.8 *

2, 3



7.8 *

2, 3

μS

0°C

≤ TCASE ≤ 85°C



7.8 *

1



7.8 *

1



7.8 *

1

μS

85°C

< TCASE

≤ 95°C



3.9 *

4



3.9 *

4



3.9 *

4

μS

95°C

< TCASE

≤ 105°C



*6



3.9 *

5, 6



3.9 *

5, 6

μS

Operating One Bank Active-Precharge Current

IDD0



130



115



105

mA

Operating One Bank Active-Read-Precharge

Current

IDD1



165



145



130

mA

Operating Burst Read Current

IDD4R



330



280



240

mA

Operating Burst Write Current

IDD4W



260



220



190

mA

Burst Refresh Current

IDD5B



185



170



160

mA

Self-Refresh Current, TOPER = 0 ~ 85°C

IDD6



14



14



14

mA

Operating Bank Interleave Current

IDD7



430



400



380

mA

Notes: (Field value contents in blue font or parentheses are optional AC parameter and CL setting)

1.

All speed grades support 0°C

≤ TCASE ≤ 85°C with full JEDEC AC and DC specifications.

2.

For -11, -12 and -15 speed grades, -40°C

≤ TCASE < 0°C is not available.

3.

12I, 12A, 12K, 15I, 15A and 15K speed grades support -40°C

≤ TCASE ≤ 85°C with full JEDEC AC and DC specifications.

4.

For all speed grade parts, TCASE is able to extend to 95°C with doubling Auto Refresh commands in frequency to a 32 mS

period ( tREFI = 3.9 µS), it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range

capability (MR2 A6 = 0b and MR2 A7 = 1b) or enable the Auto Self-Refresh mode (ASR) (MR2 A6 = 1b, MR2 A7 is don't care).

5.

For 12K and 15K automotive parts, TCASE is able to extend to 105°C with doubling Auto Refresh commands in frequency to a

32 mS period ( tREFI = 3.9 µS), it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature

Range capability (MR2 A6 = 0b and MR2 A7 = 1b) or enable the Auto Self-Refresh mode (ASR) (MR2 A6 = 1b, MR2 A7 is

don't care).

6.

For -11, -12, 12I, 12A, -15, 15I and 15A speed grade parts, 95°C < TCASE

≤ 105°C is not available.

7.

For devices supporting optional down binning to CL=7 and CL=9, tAA/tRCD/tRP min must be 13.125 nS or lower. SPD settings

must be programmed to match. For example, DDR3-1333 (9-9-9) devices supporting down binning to DDR3-1066 (7-7-7)

should program 13.125 nS in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3-1600 (11-11-11)

devices supporting down binning to DDR3-1333 (9-9-9) or DDR3-1066 (7-7-7) should program 13.125 nS in SPD bytes for

tAAmin (Byte16), tRCDmin (Byte 18), and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125 nS, tRCmin (Byte 21,

23) also should be programmed accodingly. For example, 49.125nS (tRASmin + tRPmin = 36 nS + 13.125 nS) for DDR3-1333

(9-9-9) and 48.125 nS (tRASmin + tRPmin = 35 nS + 13.125 nS) for DDR3-1600 (11-11-11).

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