W631GG6KB15K datasheet(1/158 Pages) WINBOND

Part #	W631GG6KB15K

Description	Double Data Rate architecture: two data transfers per clock cycle

Download	158 Pages

Scroll/Zoom	100%

Manufacturer	WINBOND [Winbond]

Direct Link	http://www.winbond.com

Logo

1 / 158 page

W631GG6KB

8M  8 BANKS  16 BIT DDR3 SDRAM

Publication Release Date: Feb. 27, 2013

Revision A04

- 1 -

Table of Contents-

1.

GENERAL DESCRIPTION ...................................................................................................................5

2.

FEATURES ...........................................................................................................................................5

3.

ORDER INFORMATION .......................................................................................................................6

4.

KEY PARAMETERS .............................................................................................................................7

5.

BALL CONFIGURATION ......................................................................................................................8

6.

BALL DESCRIPTION............................................................................................................................9

7.

FUNCTIONAL DESCRIPTION............................................................................................................11

7.1

Basic Functionality ..............................................................................................................................11

7.2

RESET and Initialization Procedure ....................................................................................................11

7.2.1

Power-up Initialization Sequence .....................................................................................11

7.2.2

Reset Initialization with Stable Power ..............................................................................13

7.3

Programming the Mode Registers.......................................................................................................14

7.3.1

Mode Register MR0 .........................................................................................................16

7.3.1.1

Burst Length, Type and Order ................................................................................17

7.3.1.2

CAS Latency...........................................................................................................17

7.3.1.3

Test Mode...............................................................................................................18

7.3.1.4

DLL Reset...............................................................................................................18

7.3.1.5

Write Recovery .......................................................................................................18

7.3.1.6

Precharge PD DLL .................................................................................................18

7.3.2

Mode Register MR1 .........................................................................................................19

7.3.2.1

DLL Enable/Disable ................................................................................................19

7.3.2.2

Output Driver Impedance Control ...........................................................................20

7.3.2.3

ODT RTT Values ....................................................................................................20

7.3.2.4

Additive Latency (AL) .............................................................................................20

7.3.2.5

Write leveling ..........................................................................................................20

7.3.2.6

Output Disable........................................................................................................20

7.3.3

Mode Register MR2 .........................................................................................................21

7.3.3.1

Partial Array Self Refresh (PASR) ..........................................................................22

7.3.3.2

CAS Write Latency (CWL) ......................................................................................22

7.3.3.3

Auto Self Refresh (ASR) and Self Refresh Temperature (SRT) .............................22

7.3.3.4

Dynamic ODT (Rtt_WR) .........................................................................................22

7.3.4

Mode Register MR3 .........................................................................................................23

7.3.4.1

Multi Purpose Register (MPR) ................................................................................23

7.4

No OPeration (NOP) Command..........................................................................................................24

7.5

Deselect Command.............................................................................................................................24

7.6

DLL-off Mode ......................................................................................................................................24

7.7

DLL on/off switching procedure...........................................................................................................25

7.7.1

DLL ―on‖ to DLL ―off‖ Procedure.......................................................................................25

Similar Part No. - W631GG6KB15K

Manufacturer	Part #	Datasheet	Description
Winbond	W631GU6KB-12-TR	4Mb / 160P	8M ??8 BANKS ??16 BIT DDR3L SDRAM

More results

Similar Description - W631GG6KB15K

Manufacturer	Part #	Datasheet	Description
Elite Semiconductor Mem...	M13S128324A-2M	1Mb / 48P	Double-data-rate architecture, two data transfers per clock cycle
	M13S5121632A-2S	705Kb / 48P	Double-data-rate architecture, two data transfers per clock cycle
	M13S2561616A-2S	1Mb / 49P	Double-data-rate architecture, two data transfers per clock cycle
Winbond	W9412G2IB4	832Kb / 50P	Double Data Rate architecture; two data transfers per clock cycle
Winbond	W9412G6JH-5	1Mb / 53P	Double Data Rate architecture; two data transfers per clock cycle
Elite Semiconductor Mem...	M13S2561616A-2A	1Mb / 49P	Double-data-rate architecture, two data transfers per clock cycle
Winbond	W9751G6KB-25	1Mb / 87P	Double Data Rate architecture: two data transfers per clock cycle
Elite Semiconductor Mem...	M13L32321A-2G	1Mb / 48P	Double-data-rate architecture, two data transfers per clock cycle
Elite Semiconductor Mem...	M13L2561616A-2A	1Mb / 49P	Double-data-rate architecture, two data transfers per clock cycle
Winbond	W972GG6JB-25	1Mb / 87P	Double Data Rate architecture: two data transfers per clock cycle

More results

W631GG6KB15K Datasheet(PDF) 1 Page - Winbond

W631GG6KB15K Datasheet(HTML) 1 Page - Winbond

Similar Part No. - W631GG6KB15K

Similar Description - W631GG6KB15K

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL