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W631GG6KB15K Datasheet(PDF) 1 Page - Winbond |
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W631GG6KB15K Datasheet(HTML) 1 Page - Winbond |
1 / 158 page W631GG6KB 8M 8 BANKS 16 BIT DDR3 SDRAM Publication Release Date: Feb. 27, 2013 Revision A04 - 1 - Table of Contents- 1. GENERAL DESCRIPTION ...................................................................................................................5 2. FEATURES ...........................................................................................................................................5 3. ORDER INFORMATION .......................................................................................................................6 4. KEY PARAMETERS .............................................................................................................................7 5. BALL CONFIGURATION ......................................................................................................................8 6. BALL DESCRIPTION............................................................................................................................9 7. FUNCTIONAL DESCRIPTION............................................................................................................11 7.1 Basic Functionality ..............................................................................................................................11 7.2 RESET and Initialization Procedure ....................................................................................................11 7.2.1 Power-up Initialization Sequence .....................................................................................11 7.2.2 Reset Initialization with Stable Power ..............................................................................13 7.3 Programming the Mode Registers.......................................................................................................14 7.3.1 Mode Register MR0 .........................................................................................................16 7.3.1.1 Burst Length, Type and Order ................................................................................17 7.3.1.2 CAS Latency...........................................................................................................17 7.3.1.3 Test Mode...............................................................................................................18 7.3.1.4 DLL Reset...............................................................................................................18 7.3.1.5 Write Recovery .......................................................................................................18 7.3.1.6 Precharge PD DLL .................................................................................................18 7.3.2 Mode Register MR1 .........................................................................................................19 7.3.2.1 DLL Enable/Disable ................................................................................................19 7.3.2.2 Output Driver Impedance Control ...........................................................................20 7.3.2.3 ODT RTT Values ....................................................................................................20 7.3.2.4 Additive Latency (AL) .............................................................................................20 7.3.2.5 Write leveling ..........................................................................................................20 7.3.2.6 Output Disable........................................................................................................20 7.3.3 Mode Register MR2 .........................................................................................................21 7.3.3.1 Partial Array Self Refresh (PASR) ..........................................................................22 7.3.3.2 CAS Write Latency (CWL) ......................................................................................22 7.3.3.3 Auto Self Refresh (ASR) and Self Refresh Temperature (SRT) .............................22 7.3.3.4 Dynamic ODT (Rtt_WR) .........................................................................................22 7.3.4 Mode Register MR3 .........................................................................................................23 7.3.4.1 Multi Purpose Register (MPR) ................................................................................23 7.4 No OPeration (NOP) Command..........................................................................................................24 7.5 Deselect Command.............................................................................................................................24 7.6 DLL-off Mode ......................................................................................................................................24 7.7 DLL on/off switching procedure...........................................................................................................25 7.7.1 DLL ―on‖ to DLL ―off‖ Procedure.......................................................................................25 |
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