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ADP5050ACPZ-R7 Datasheet(PDF) 9 Page - Analog Devices |
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ADP5050ACPZ-R7 Datasheet(HTML) 9 Page - Analog Devices |
9 / 60 page Data Sheet ADP5050 Rev. 0 | Page 9 of 60 I2C INTERFACE TIMING SPECIFICATIONS TA = 25°C, VVDD = 3.3 V, VVDDIO = 3.3 V, unless otherwise noted. Table 4. Parameter Min Typ Max Unit Description fSCL 400 kHz SCL clock frequency tHIGH 0.6 µs SCL high time tLOW 1.3 µs SCL low time tSU,DAT 100 ns Data setup time tHD,DAT 0 0.9 µs Data hold time1 tSU,STA 0.6 µs Setup time for a repeated start condition tHD,STA 0.6 µs Hold time for a start or repeated start condition tBUF 1.3 µs Bus free time between a stop condition and a start condition tSU,STO 0.6 µs Setup time for a stop condition tR 20 + 0.1CB2 300 ns Rise time of SCL and SDA tF 20 + 0.1CB2 300 ns Fall time of SCL and SDA tSP 0 50 ns Pulse width of suppressed spike CB2 400 pF Capacitive load for each bus line 1 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH minimum of the SCL signal) to bridge the undefined region of the SCL falling edge. 2 CB is the total capacitance of one bus line in picofarads (pF). Timing Diagram S S P Sr S = START CONDITION Sr = REPEATED START CONDITION P = STOP CONDITION SCL SDA tHD,DAT tSU,DAT tHD,STA tSU,STA tSU,STO tHIGH tR tF tF tSP tR tLOW tBUF Figure 3. I2C Interface Timing Diagram |
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