Electronic Components Datasheet Search |
|
ADRF6518ACPZ-R7 Datasheet(PDF) 7 Page - Analog Devices |
|
ADRF6518ACPZ-R7 Datasheet(HTML) 7 Page - Analog Devices |
7 / 36 page Preliminary Technical Data ADRF6518 Rev. PrA | Page 7 of 36 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 4. Pin Configuration Table 3. Pin Function Descriptions Pin No. Mnemonic Description 1 VPSD Digital Positive Supply Voltage: 3.15 V to 3.45 V. 2 COMD Digital Common. Connect to external circuit common using the lowest possible impedance. 3 LE Latch Enable. SPI programming pin. TTL levels: VLOW < 0.8 V, VHIGH > 2 V. 4 CLK SPI Port Clock. TTL levels: VLOW < 0.8 V, VHIGH > 2 V. 5 DATA SPI Data Input. TTL levels: VLOW < 0.8 V, VHIGH > 2 V. 6 SDO/RST SPI Data Output (SDO). TTL levels: VLOW < 0.8 V, VHIGH > 2 V. Peak Detector Reset (RST). A >25 ns high pulse is required on this pin to reset the detector. 7 VICM/AC Input Common-Mode Reference (VICM). VPI/2 reference output for optimal common-mode level to drive the differential inputs. AC Coupling/Internal Bias Activation (AC). Pull this pin low for ac coupling of the inputs. 8 VPI Input Stage Supply Voltage: 3.15 V to 5.25 V. Connect to VPS if input common-mode range is narrow (1.35 V to 1.95 V). Connect to 5 V if input common-mode up to 3.1 V is desired. 12, 16, 25, 29 VPS Analog Positive Supply Voltage: 3.15 V to 3.45 V. 9, 19, 22 COM Analog Common. Connect to external circuit common using the lowest possible impedance. 10, 11, 30, 31 INP2, INM2, INM1, INP1 Differential Inputs. 400 Ω input impedance. 13 VPK Peak Detector Output. Scaling of 1 V/V pk differential at filter inputs. The bigger peak of two channels is reported. 14 VGN2 VGA2 Analog Gain Control. 0 V to 1 V, 30 mV/dB gain scaling. 15, 26 OFS2, OFS1 Offset Correction Loop Compensation Capacitors. Connect capacitors to circuit common. 17, 18, 23, 24 OPP2, OPM2, OPM1, OPP1 Differential Outputs. <10 Ω output impedance. Common-mode range is 0.9 V to VPS − 1.2 V; default is VPS/2. 20 VOCM Output Common-Mode Setpoint. Defaults to VPS/2 if left open. 21 VGN3 VGA3 Analog Gain Control. 0 V to 1 V, 30 mV/dB gain scaling. 27 VGN1 VGA1 Analog Gain Control. 0 V to 1 V, 30 mV/dB gain scaling. 28 RAVG Peak Detector Time-Constant Resistor. Connect this pin to VPS. Leave open for longest hold time. RAVG range is ∞ to 1 kΩ. 32 ENBL Chip Enable. Pull high to enable. EP Exposed Pad. Connect the exposed pad to a low impedance ground pad. |
Similar Part No. - ADRF6518ACPZ-R7 |
|
Similar Description - ADRF6518ACPZ-R7 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |