Package Differences

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Table 2. LS31x/21x and LS20x/10x Ball-Map Differences (continued)

337 BGA Ball# for

337 BGA Ball# for

Signal Name

LS20x/10x

LS31x/21x

EMIF_nCS[5] (asynchronous chip select)

N17

–

EMIF_nCS[0] (SDRAM chip select)

–

N17

RAM Trace Port (RTP) Differences

RTPDATA[0]

V11

NC

RTPDATA[1]

U11

NC

RTPDATA[2]

T10

NC

RTPDATA[3]

U10

NC

RTPDATA[4]

T9

NC

RTPDATA[5]

U9

NC

RTPDATA[6]

U8

NC

RTPDATA[7]

U7

NC

RTPDATA[8]

U6

NC

RTPDATA[9]

U5

NC

RTPDATA[10]

U4

NC

RTPDATA[11]

T4

NC

RTPDATA[12]

V3

NC

RTPDATA[13]

U3

NC

RTPDATA[14]

T3

NC

RTPDATA[15]

T2

NC

RTPnENA

U12

NC

RTPSYNC

T11

NC

RTPCLK

W11

NC

Local Interconnect Network (LIN) Interface Differences

LIN1 TX

V12

NC

LIN1 RX

W12

NC

LIN2 TX

B7

B7

LIN2 RX

A7

A7

Important Note: The control and status registers for the LIN module on LS31x/21x are mapped to the same location as the

LIN1 module on LS20x/10x.

Standard Serial Peripheral Interface (SPI2) Differences

SPI2 CLK

NC

E2

SPI2 SIMO

NC

D1

SPI2 SOMI

NC

D2

SPI2 nCS[0]

NC

N3

SPI2 nENA

NC

D3

4.2.1

External Memory Interface (EMIF)

The EMIF on LS31x/21x supports interfacing to an external SDRAM in addition to asynchronous

memories. Therefore, the EMIF on the LS31x/21x microcontrollers has additional signals to interface to an

external SDRAM.

Also, some EMIF signals are multiplexed with Embedded Trace Macrocell (ETM) signals on the

LS31x/21x microcontrollers. As a result, the full EMIF port is not available at the same time as the full

ETM port. The LS20x/10x microcontrollers has no multiplexing between EMIF/ETM signals. This causes

an incompatibility in the ball mapping for the EMIF signals between LS31x/21x and LS20x/10x.

8

Compatibility Considerations: TMS570LS20x/10x to TMS570LS31x/21x

SPNA135A

– October 2011

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