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AD7621ASTRL Datasheet(PDF) 6 Page - Analog Devices

Part # AD7621ASTRL
Description  16-Bit, 2 LSB INL, 3 MSPS PulSAR짰 ADC
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7621ASTRL Datasheet(HTML) 6 Page - Analog Devices

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AD7621
Rev. 0 | Page 6 of 32
Parameter
Symbol
Min
Typ
Max
Unit
SLAVE SERIAL INTERFACE MODES5 (Refer to Figure 40 and Figure 41)
External SCLK Setup Time
t31
5
ns
External SCLK Active Edge to SDOUT Delay
t32
1
8
ns
SDIN Setup Time
t33
5
ns
SDIN Hold Time
t34
5
ns
External SCLK Period
t35
12.5
ns
External SCLK High
t36
5
ns
External SCLK Low
t37
5
ns
1 See the Conversion Control section.
2 All timings for wideband warp mode are the same as warp mode.
3 In warp mode only, the time between conversions is 1 ms; otherwise, there is no required maximum time.
4 See the Digital Interface, and RESET sections.
5 In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
6 In serial master read during convert mode. See Table 4 for serial master read after convert mode timing specifications.
SERIAL CLOCK TIMING SPECIFICATIONS
Table 4. Serial Clock Timings in Master Read After Convert Mode
DIVSCLK[1]
0
0
1
1
DIVSCLK[0]
Symbol
0
1
0
1
Unit
SYNC to SCLK First Edge Delay Minimum
t18
0.5
3
3
3
ns
Internal SCLK Period Minimum
t19
8
16
32
64
ns
Internal SCLK Period Maximum
t19
12
25
50
100
ns
Internal SCLK High Minimum
t20
2
6
15
31
ns
Internal SCLK Low Minimum
t21
3
7
16
32
ns
SDOUT Valid Setup Time Minimum
t22
1
5
5
5
ns
SDOUT Valid Hold Time Minimum
t23
0
0.5
10
28
ns
SCLK Last Edge to SYNC Delay Minimum
t24
0
0.5
9
26
ns
BUSY High Width Maximum (Wideband and Warp Modes)
t28
0.500
0.720
1.160
2.040
μs
BUSY High Width Maximum (Normal Mode)
t28
0.650
0.870
1.310
2.190
μs
BUSY High Width Maximum (Impulse Mode)
t28
0.780
1.000
1.440
2.320
μs
NOTE
IN SERIAL INTERFACE MODES, THE SYNC, SCLK AND
SDOUT ARE DEFINED WITH A MAXIMUM LOAD.
CL OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
500
μAI
OL
500
μAI
OH
1.4V
TO OUTPUT
PIN
CL
50pF
Figure 2. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, and SCLK Outputs, CL = 10 pF
0.8V
2V
2V
0.8V
0.8V
2V
tDELAY
tDELAY
Figure 3. Voltage Reference Levels for Timing


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