ADM3101E

Rev. C | Page 8 of 12

THEORY OF OPERATION

The ADM3101E is a single-channel RS-232 line driver/receiver.

Step-up voltage converters, coupled with level shifting trans-

mitters and receivers, allow RS-232 levels to be developed while

operating from a single 3.3 V supply.

CMOS technology is used to keep the power dissipation to

an absolute minimum, allowing maximum battery life in

portable applications.

CIRCUIT DESCRIPTION

The internal circuitry consists of the following main sections:

•

A charge pump voltage converter

•

A 3.3 V logic to an EIA/TIA-232E transmitter

•

An EIA/TIA-232E to a 3.3 V logic receiver

ADM3101E

GND

+3.3V INPUT

+

+

+

C1

0.1µF

16V

C2

0.1µF

16V

T

R

+3.3V TO +6.6V

VOLTAGE DOUBLER

+6.6V TO –6.6V

VOLTAGE INVERTER

C1+

C1–

C2+

C2–

CMOS

INPUT

CMOS

OUTPUT

V+

V–

C5

0.1µF

C3

0.1µF

6.3V

C4

0.1µF

16V

EIA/TIA-232E

OUTPUT

EIA/TIA-232E

INPUT*

*INTERNAL 5kΩ PULL-DOWN

RESISTOR ON THE RS-232 INPUT.

Figure 12. Typical Operating Circuit

Charge Pump Voltage Converter

The charge pump voltage converter consists of a 200 kHz oscil-

lator and a switching matrix. The converter generates a ±6.6 V

supply (when unloaded) from the 3.3 V input level. This is achieved

in two stages by using a switched capacitor technique, as illustrated

in Figure 13 and Figure 14. First, the 3.3 V input supply is doubled

to +6.6 V by using C1 as the charge storage element. The +6.6 V

level is then inverted to generate −6.6 V using C2 as the storage

equally effective if connected between V+ and GND.

The C3 and C4 capacitors are used to reduce the output ripple.

The values are not critical and can be increased, if desired. Larger

capacitors (up to 10 μF) can also be used in place of the C1, C2,

C3, and C4 capacitors.

GND

C3

C1

S1

S2

S3

S4

+

+

INTERNAL

OSCILLATOR

Figure 13. Charge Pump Voltage Doubler

GND

C4

C2

S1

S2

S3

S4

GND

+

+

INTERNAL

OSCILLATOR

V+

V– = –(V+)

FROM

VOLTAGE

DOUBLER

Figure 14. Charge Pump Voltage Inverter

3.3 V Logic to EIA/TIA-232E Transmitter

The transmitter driver converts the 3.3 V logic input levels

into RS-232 output levels. When driving an RS-232 load with

open-drain output, but the maximum operating data rate is

EIA/TIA-232E to 3.3 V Logic Receiver

The receiver is an inverting level shifter that accepts the RS-232

input level and translates it into a 3.3 V logic output level. The

input has an internal 5 kΩ pull-down resistor to ground and is

protected against overvoltages of up to ±30 V. An unconnected

input is pulled to 0 V by the internal 5 kΩ pull-down resistor,

which, therefore, results in a Logic 1 output level for an uncon-

nected input or for an input connected to GND.

The receiver has a Schmitt trigger input with a hysteresis level

of 0.4 V, which ensures error-free reception for both a noisy

input and for an input with slow transition times.

CMOS Input Voltage Thresholds

ADM3101E are designed to interface with 1.8 V logic

ADM3101E are also designed to interface with TTL/CMOS

ESD Protection on RS-232 and CMOS I/O Pins

and outputs are protected against electrostatic discharges (up

to ±15 kV).

HIGH BAUD RATE

The ADM3101E features high slew rates, permitting data trans-

mission at rates well in excess of the EIA/RS-232 specifications.

The RS-232 voltage levels are maintained at data rates of up to

driven by a push-pull output. The slew rate is internally controlled

to less than 30 V/μs to minimize EMI interference.