A3992_13 datasheet(4/13 Pages) ALLEGRO

Part #	A3992

Description	DMOS Dual Full-Bridge Microstepping PWM Motor Driver

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Manufacturer	ALLEGRO [Allegro MicroSystems]

Direct Link	http://www.allegromicro.com

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4 / 13 page

DMOS Dual Full-Bridge

Microstepping PWM Motor Driver

A3992

4

Allegro MicroSystems, LLC

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

ELECTRICAL CHARACTERISTICS1 valid at TA= 25°C, VBB = 50 V, fPWM < 50 kHz, unless otherwise noted

Characteristic

Symbol

Test Conditions

Min.

Typ.2

Max.

Units

Output Drivers

Load Supply Voltage Range

VBB

Operating, IOUT = ±1.5 A

15

–

50

V

During Sleep mode

0

–

50

V

Output Leakage Current

IDSS

VOUT = VBB

–

<1.0

50

μA

VOUT = 0 V

–

<–1.0

–50

μA

Output On Resistance

RDS(on)

Source driver, IOUT = -1.5 A

–

0.54

0.6

Ω

Sink driver, IOUT = 1.5 A

–

0.54

0.6

Ω

Body Diode Forward Voltage

VF

Source diode, IF = -1.5 A

–

1.2

V

Sink diode, IF = 1.5 A

–

1.2

V

Motor Supply Current

IBB

fPWM < 50 kHz

–

8

mA

Operating, outputs disabled

–

6

mA

Sleep or Idle mode

–

20

μA

Logic Supply Current

IDD

fPWM < 50 kHz

–

12

mA

Outputs off

–

10

mA

Idle mode (Word 1, D18 = 0)

–

1.5

mA

Sleep mode

–

100

μA

Control Logic

Logic Supply Voltage Range

VDD

Operating

4.5

5

5.5

V

Logic Input Voltage

VIN(1)

2.0

–

V

VIN(0)

–

0.8

V

Logic Input Current

IIN(1)

VIN = 2.0 V

–

<1.0

20

μA

IIN(0)

VIN = 0.8 V

–

<–2.0

–20

μA

Input Hysteresis

0.20

–

0.40

V

Minimum sleep pulse width

tS

> 2

–

μs

OSC input frequency

fOSC(in)

Divide by 1 (Word 2, D13=0, D14=1)

2.5

–

6

MHz

OSC input duty cycle

40

–

60

%

Internal Oscillator

fOSC

OSC shorted to GND

3

4

5

MHz

ROSC= 51 kΩ

3.4

4

4.6

MHz

DAC Accuracy

VDAC

Measured relative to REF buffer output

–

±0.5

–

LSB

Reference Input Voltage Range

.5

–

2.6

V

Reference Buffer Offset

VOS

–

±10

–

mV

Reference Divider Ratio

VREF/VSENSE

Word 0, D18 = 0, D17 = 1, VREF = 0.5 to 2.6 V

7.4

8

8.8

–

Word 0, D18 = 1, D17 = 1, VREF =0.5 to 2.6 V

3.6

4

4.4

–

Reference Input Current

IREF

VREF = 2.0 V

–0.5

–

0.5

μA

Internal Reference Voltage

VREFINT

1.940

2.0

2.060

V

Comparator Input Offset Volt.

VIO

VREF = 0 V

–5

0

5

mV

GM Error3

VERR

Internal VREF, Range = 8, DAC = 63

–6

0

6

%

Internal VREF, Range = 8, DAC = 31

–9

0

9

%

Internal VREF, Range = 4, DAC = 63

–6

0

6

%

Internal VREF, Range = 4, DAC = 15

–10

0

10

%

Propagation Delay Times

tpd

50% to 90%; PWM change to source on

500

800

1000

ns

50% to 90%; PWM change to source off

35

–

250

ns

50% to 90%; PWM change to sink on

500

800

1000

ns

50% to 90%; PWM change to sink off

35

–

250

ns

Crossover Dead Time

tDT

300

650

900

ns

UVLO Enable Threshold

VUVLO

VDD rising

3.9

4.2

4.45

V

UVLO Hysteresis

VUVLOHYS

0.05

0.10

–

V

Protection Circuitry

Overcurrent Protection Threshold4

IOCPST

2–

–

A

Overcurrent Blanking

tOCP

1–

3

μs

Thermal Shutdown Temperature

TJ

–

165

–

°C

Thermal Shutdown Hysteresis

TJHYS

–15

–

°C

1

Negative current is deﬁned as coming out of (sourcing) the speciﬁed device pin.

2

Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for

individual units, within the speciﬁed maximum and minimum limits.

3

VERR = [(VREF/Range) – VSENSE] /(VREF/Range).

4

OCP is tested at TA = 25°C in a restricted range and guaranteed by characterization.

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