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AD5271BRMZ-20-RL7 Datasheet(PDF) 10 Page - Analog Devices |
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AD5271BRMZ-20-RL7 Datasheet(HTML) 10 Page - Analog Devices |
10 / 24 page AD5270/AD5271 Data Sheet Rev. F | Page 10 of 24 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VDD 11 VSS 2 2 A 3 3 W 4 4 SDO 10 9 8 SCLK 7 5 EXT_CAP DIN 6 GND AD5270/ AD5271 TOP VIEW (Not to Scale) SYNC Figure 5. MSOP Pin Configuration SYNC VDD 1 VSS 2 A 3 W 4 SDO 10 9 8 SCLK 7 5 EXT_CAP DIN 6 GND NOTES 1. THE EXPOSED PAD IS LEFT FLOATING OR IS TIED TO VSS. AD5270/ AD5271 (EXPOSED PAD) Figure 6. LFCSP Pin Configuration Table 10. Pin Function Descriptions Pin No. Mnemonic Description 1 VDD Positive Power Supply. Decouple this pin with 0.1 μF ceramic capacitors and 10 μF capacitors. 2 A Terminal A of RDAC. VSS ≤ VA ≤ VDD. 3 W Wiper Terminal of RDAC. VSS ≤ VW ≤ VDD. 4 VSS Negative Supply. Connect to 0 V for single-supply applications. Decouple this pin with 0.1 μF ceramic capacitors and 10 μF capacitors. 5 EXT_CAP External Capacitor. Connect a 1 μF capacitor between EXT_CAP and VSS. This capacitor must have a voltage rating of ≥7 V. 6 GND Ground Pin, Logic Ground Reference. 7 SDO Serial Data Output. This pin can be used to clock data from the shift register in daisy-chain mode or in readback mode. This open-drain output requires an external pull-up resistor even if it is not use. 8 DIN Serial Data Line. This pin is used in conjunction with the SCLK line to clock data into or out of the 16-bit input register. 9 SCLK Serial Clock Input. Data is clocked into the shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 50 MHz. 10 SYNC Falling Edge Synchronization Signal. This is the frame synchronization signal for the input data. When SYNC goes low, it enables the shift register and data is transferred in on the falling edges of the subsequent clocks. The selected register is updated on the rising edge of SYNC following the 16th clock cycle. If SYNC is taken high before the 16th clock cycle, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the RDAC. EPAD Exposed Pad Leave floating or connected to VSS. |
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