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AD9826KRSZ Datasheet(PDF) 10 Page - Analog Devices |
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AD9826KRSZ Datasheet(HTML) 10 Page - Analog Devices |
10 / 20 page AD9826 –10– tAD PIXEL n (R,G,B) tC2 tADCLK tADCLK tC2ADR ANALOG INPUTS CDSCLK2 ADCCLK OUTPUT DATA D<7:0> R (n–1) tC2AD tADC2 HIGH BYTE LOW BYTE tOD tPRA HB LB HB HB HB HB HB LB LB LB LB LB R (n–2) G (n–2) G (n–2) B (n–2) B (n–2) R (n–1) G (n–1) G (n–1) B (n–1) B (n–1) R (n) R (n) G (n) G (n) PIXEL (n+1) Figure 5. 3-Channel SHA Mode Timing HIGH BYTE LOW BYTE LOW BYTE LOW BYTE HIGH BYTE HIGH BYTE ANALOG INPUTS CDSCLK2 ADCCLK OUTPUT DATA D<7:0> PIXEL n tAD tC2ADR tOD tPRB PIXEL (n–4) PIXEL (n–4) PIXEL (n–3) PIXEL (n–3) PIXEL (n–2) PIXEL (n–2) tC2ADF tADCLK tC2 tADCLK tADCLK NOTE IN 1-CHANNEL SHA MODE,THE CDSCLK2 RISING EDGE MUST OCCUR WHILE ADCCLK IS “LOW.” Figure 6. 1-Channel SHA Mode Timing REV. B |
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