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BD37Axx Series

BD87Axx Series

BD99A41F

Datasheet

TSZ02201-0T2T0AN00130-1-2

© 2013 ROHM Co., Ltd. All rights reserved.

25.Apr.2013 Rev.002

www.rohm.com

TSZ22111・15・001

●Timing chart

Figure 15. Timing Chart

●Explanation

①

The RESET pin voltage (RESET) switches to low when the power supply voltage (VDD) falls to 0.8 V.

②

The external capacitor connected to the CT pin begins to charge when VDD rises above the reset detection voltage

(VDETH). The RESET signal stays low until VDD reaches the VDETH voltage and switches to high when VDD reaches

or exceeds the VDETH voltage. The RESET transmission delay time TPLH allowed to elapse before RESET switches

from low to high is given by the following equation:

TPLH (s)

 0.69 × Rrst × CT (µF)   [1]

Rrst denotes the IC's built-in resistance and is designed to be 10 M

Ω (Typ.). CT denotes the external capacitor

connected to the CT pin.

③

The external capacitor connected to the CTW pin begins to charge when RESET rises, triggering the watchdog timer.

④

The CTW pin state switches from charge to discharge when the CTW pin voltage (VCTW) reaches VthH, and RESET

switches from high to low. The watchdog timer monitor time TWH is given by the following equation:

TWH (s)

 (0.5 × CTW (µF))/(ICTWC)   [2]

ICTWC denotes the CTW charge current and is designed to be 0.50 µA (Typ.). CTW denotes the external capacitor

connected to the CTW pin.

⑤

The CTW pin state switches from charge to discharge when VCTW reaches VthL, and RESET switches from low to

high. The watchdog timer reset time TWL is given by the following equation:

TWL (s)

 (0.5 × CTW (µF))/(ICTWO)   [3]

ICTWO denotes the CTW discharge current and is designed to be 1.50 µA (Typ.).

⑥

The CTW pin state may not switch from charge to discharge when the CLK input pulse width TWCLK is short. Use a

TWCLK input pulse width of at least 500 ns.

TWCLK

≥ 500 ns (Min.)

⑦

When a pulse (positive edge trigger) of at least 500 ns is input to the CLK pin while the CTW pin is charging, the CTW

state switches from charge to discharge. Once it discharges to VthL, it will charge again.

⑧ Watchdog timer operation is forced off when the INH pin switches to low (L: BD37Axx Series. BD99A41F, H:

BD87AxxSeries). At that time, only the watchdog timer is turned off. Reset detection is performed normally.

⑨

The watchdog timer function turns on when the INH pin switches to high(H: BD37Axx Series. BD99A41F, L:

BD87AxxSeries). The external capacitor connected to the CTW pin begins to charge at that time.

⑩

RESET switches from high to low when VDD falls to the RESET detection voltage (VDET) or lower.

⑪

When VDD falls to 0 V, the RESET signal stays low until VDD reaches 0.8 V.

⑦

④

⑤

*2

(BD37AxxFVM／BD99A41F)

⑤

⑥

⑤

⑦

④ ⑤⑧

⑨

⑩

③

③

⑪

⑩

④

②

⑤ ⑩ ②

④ ⑤

④

④

INH

VCTW

CLK

RESET

①②③

0

0

0

0

0

WDT circuit turns off when INH is high

TWCLK

*4 TWCLK

VthH

VthL

*1

TPLH

*3

TWL

TWH

VCT VCTH

INH

VDD

VDETH

VDET

WDT circuit turns off when INH is low

0

0

VDETH=VDET+Vrhys

(BD87AxxFVM)