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BS83A04A-3 Datasheet(PDF) 10 Page - Holtek Semiconductor Inc |
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BS83A04A-3 Datasheet(HTML) 10 Page - Holtek Semiconductor Inc |
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10 / 72 page  Rev. 1.00 10 �e���a�� ��� �01� Rev. 1.00 11 �e���a�� ��� �01� BS83A04A-3/BS83A04A-4 8-bit Touch Key Flash MCU System Architecture Akeyfactorinthehigh-performancefeaturesoftheHoltekrangeofmicrocontrollersisattributed totheirinternalsystemarchitecture.Therangeofdevicetakesadvantageoftheusualfeaturesfound withinRISCmicrocontrollersprovidingincreasedspeedofoperationandenhancedperformance. Thepipeliningschemeisimplementedinsuchawaythatinstructionfetchingandinstruction executionareoverlapped,henceinstructionsareeffectivelyexecutedinonecycle,withthe exceptionofbranchorcallinstructions.An8-bitwideALUisusedinpracticallyallinstructionset operations,whichcarriesoutarithmeticoperations,logicoperations,rotation,increment,decrement, branchdecisions,etc.TheinternaldatapathissimplifiedbymovingdatathroughtheAccumulator andtheALU.CertaininternalregistersareimplementedintheDataMemoryandcanbedirectly orindirectlyaddressed.Thesimpleaddressingmethodsoftheseregistersalongwithadditional architecturalfeaturesensurethataminimumofexternalcomponentsisrequiredtoprovidea functionalI/Owithmaximumreliabilityandflexibility.Thismakesthedevicesuitableforlow-cost, high-volumeproductionforcontrollerapplications. Clocking and Pipelining Themiansystemclock,derivedfromHIRCorLIRCoscillatorissubdividedintofourinternally generatednon-overlappingclocks,T1~T4.TheProgramCounterisincrementedatthebeginning oftheT1clockduringwhichtimeanewinstructionisfetched.TheremainingT2~T4clockscarry outthedecodingandexecutionfunctions.Inthisway,oneT1~T4clockcycleformsoneinstruction cycle.Althoughthefetchingandexecutionofinstructionstakesplaceinconsecutiveinstruction cycles,thepipeliningstructureofthemicrocontrollerensuresthatinstructionsareeffectively executedinoneinstructioncycle.Theexceptiontothisareinstructionswherethecontentsofthe ProgramCounterarechanged,suchassubroutinecallsorjumps,inwhichcasetheinstructionwill takeonemoreinstructioncycletoexecute. Fe tc h In st . ( PC ) Ex ec ut e In st . (P C- 1) Fe tc h In st . (P C+ 1) Ex ec ut e In st . (P C) Fe tc h In st . (P C+ 2) Ex ec ut e In st . (P C+ 1) PC PC +1 PC +2 O sci ll at or C lo ck (S yst em C lo ck) P has e Cl o ck T 1 Pr og ra m C oun te r P has e Cl o ck T 2 P has e Cl o ck T 3 P has e Cl o ck T 4 Pi pel in in g System Clocking and Pipelining Forinstructionsinvolvingbranches,suchasjumporcallinstructions,twoinstructioncyclesare requiredtocompleteinstructionexecution.Anextracycleisrequiredastheprogramtakesone cycletofirstlyobtaintheactualjumporcalladdressandthenanothercycletoactuallyexecutethe branch.Therequirementforthisextracycleshouldbetakenintoaccountbyprogrammersintiming sensitiveapplications. |
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