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HT49RA0-6 Datasheet(PDF) 7 Page - Holtek Semiconductor Inc |
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HT49RA0-6 Datasheet(HTML) 7 Page - Holtek Semiconductor Inc |
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7 / 49 page  HT49RA0-6 Rev. 1.10 7 February 18, 2013 Functional Description Execution Flow The main system clock is derived from either an external crystal oscillator which requires the connection of the external crystal or resonator or an internal RC oscillator which requires no external component for its operation. It is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cy- cles. Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while de- coding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruc- tion to effectively execute within one cycle. If an instruc- tion changes the program counter, two cycles are required to complete the instruction. Program Counter - PC The program counter (PC) is 11 bits wide and controls the sequence in which the instructions stored in the pro- gram ROM are executed. The contents of the PC can specify a maximum of 2048 addresses. After accessing a program memory word to fetch an in- struction code, the value of the PC is incremented by one. The PC then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip ex- ecution, loading a PCL register, a subroutine call, an ini- tial reset, an internal interrupt, an external interrupt, or returning from a subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction. The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get a proper instruction; oth- erwise proceed with the next instruction. T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 F e t c h I N S T ( P C ) E x e c u t e I N S T ( P C - 1 ) F e t c h I N S T ( P C + 1 ) E x e c u t e I N S T ( P C ) F e t c h I N S T ( P C + 2 ) E x e c u t e I N S T ( P C + 1 ) P C P C + 1 P C + 2 S y s t e m C l o c k I n s t r u c t i o n C y c l e P C Execution Flow Mode Program Counter *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 Initial Reset 00000000000 External Interrupt 0 00000000100 External Interrupt 1 00000001000 Timer/Event Counter overflow 00000001100 Time Base Interrupt 00000010000 RTC Interrupt 00000010100 Skip Program Counter + 2 Loading PCL *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0 Jump, Call Branch #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 Return From Subroutine S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 Program Counter Note: *10~*0: Program counter bits S10~S0: Stack register bits #10~#0: Instruction code bits @7~@0: PCL bits |
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