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HT68F30-1 Datasheet(PDF) 2 Page - Holtek Semiconductor Inc |
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HT68F30-1 Datasheet(HTML) 2 Page - Holtek Semiconductor Inc |
2 / 196 page Rev. 1.10 � �an�a�� 1�� �01� Rev. 1.10 � �an�a�� 1�� �01� HT66F30-1/HT68F30-1 Enhanced Flash Type 8-Bit MCU with EEPROM HT66F30-1/HT68F30-1 Enhanced Flash Type 8-Bit MCU with EEPROM Table of Contents Features............................................................................................................ 7 CPU Feat��es ......................................................................................................................... � Pe�iphe�al Feat��es................................................................................................................. 8 General Description......................................................................................... 9 Selection Table................................................................................................. 9 Block Diagram................................................................................................ 10 Pin Assignment...............................................................................................11 Pin Description .............................................................................................. 13 Absolute Maximum Ratings.......................................................................... 15 D.C. Characteristics (HT66F30-1)................................................................. 15 A.C. Characteristics (HT66F30-1)................................................................. 17 A/D Converter Characteristics (HT66F30-1)................................................ 18 D.C. Characteristics (HT68F30-1)................................................................. 18 A.C. Characteristics (HT68F30-1)................................................................. 20 Comparator Electrical Characteristics (HT66F30-1/HT68F30-1)................ 21 Power on Reset Electrical Characteristics (HT66F30-1/HT68F30-1)......... 21 System Architecture...................................................................................... 22 Clocking and Pipelining......................................................................................................... �� P�og�am Co�nte�................................................................................................................... �� Stack ..................................................................................................................................... �4 A�ithmetic and Logic Unit – ALU ........................................................................................... �4 Flash Program Memory................................................................................. 25 St��ct��e................................................................................................................................ �5 Special Vecto�s ..................................................................................................................... �5 Look-�p Table........................................................................................................................ �5 Table P�og�am Example........................................................................................................ �6 In Ci�c�it P�og�amming ......................................................................................................... �� RAM Data Memory......................................................................................... 28 St��ct��e................................................................................................................................ �8 Special Function Register Description........................................................ 31 Indi�ect Add�essing Registe�s – IAR0� IAR1 ......................................................................... �1 Memo�� Pointe�s – MP0� MP1 .............................................................................................. �1 Bank Pointe� – BP................................................................................................................. �� Acc�m�lato� – ACC............................................................................................................... �� P�og�am Co�nte� Low Registe� – PCL.................................................................................. �� Look-�p Table Registe�s – TBLP� TBHP� TBLH..................................................................... �� Stat�s Registe� – STATUS.................................................................................................... �� |
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