FIN1026MTC datasheet(3/5 Pages) FAIRCHILD

Part #	FIN1026MTC

Description	3.3V LVDS 2-Bit High Speed Differential Receiver

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Manufacturer	FAIRCHILD [Fairchild Semiconductor]

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AC Electrical Characteristics

Over supply voltage and operating temperature ranges, unless otherwise specified

Note 3: All typical values are at TA = 25°C and with VCC = 3.3V.

Note 4: tSK(LH), tSK(HL) is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direc-

tion.

Note 5: tSK(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction

(either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits.

Note 6: fMAX Criteria: Input tR = tF < 1 ns, VID = 300 mV, (1.05V to 1.35V pp), 50% duty cycle; Output duty cycle 40% to 60%, VOL < 0.5V, VOH > 2.4V.

All channels switching in phase.

Note A: All differential input pulses have frequency

= 10MHz, t

R or tF = 1ns

FIGURE 1. Differential Receiver Voltage Definitions

Symbol

Parameter

Test Conditions

Min

Typ

Max

Units

(Note 3)

tPLH

Propagation Delay LOW-to-HIGH

1.0

2.5

ns

tPHL

Propagation Delay HIGH-to-LOW

1.0

2.5

ns

tTLH

Output Rise Time (20% to 80%)

0.7

1.2

ns

tTHL

Output Fall Time (80% to 20%)

|VID| = 400 mV, CL = 10 pF

0.7

1.2

ns

tSK(P)

Pulse Skew |tPLH - tPHL|

See Figure 1 and Figure 2

0.4

ns

tSK(LH)

Channel-to-Channel Skew

0.3

ns

tSK(HL)

(Note 4)

tSK(PP)

Part-to-Part Skew (Note 5)

1.0

ns

fMAX

Maximum Operating Frequency (Note 6)

200

375

MHz

tPZH

LVTTL Output Enable Time from Z to HIGH

6.0

ns

tPZL

LVTTL Output Enable Time from Z to LOW

RL = 1kΩ, CL = 10 pF,

6.0

ns

tPHZ

LVTTL Output Disable Time from HIGH to Z

See Figure 3

6.0

ns

tPLZ

LVTTL Output Disable Time from LOW to Z

6.0

ns

CIN

Input Capacitance

Enable Inputs

3.0

pF

RIN Inputs

4.2

COUT

Output Capacitance

6pF

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