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AD7928BRUZ Datasheet(PDF) 11 Page - Analog Devices |
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AD7928BRUZ Datasheet(HTML) 11 Page - Analog Devices |
11 / 32 page AD7908/AD7918/AD7928 Rev. D | Page 11 of 32 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 AD7908/ AD7918/ AD7928 TOP VIEW (Not to Scale) SCLK 20 2 DIN 19 3 CS DOUT 18 4 AGND AGND AGND AGND 17 5 AVDD AVDD VDRIVE REFIN 16 615 714 813 9 VIN7 VIN6 VIN0 VIN1 VIN2 VIN3 VIN4 VIN5 12 10 11 Figure 3. Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Description 1 SCLK Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the clock source for the conversion process of the AD7908/AD7918/AD7928. 2 DIN Data In. Logic input. Data to be written to the control register of the AD7908/AD7918/AD7928 is provided on this input and is clocked into the register on the falling edge of SCLK (see the Control Register section). 3 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7908/AD7918/AD7928, and also frames the serial data transfer. 4, 8, 17, 20 AGND Analog Ground. This is the ground reference point for all analog circuitry on the AD7908/AD7918/AD7928. All analog input signals and any external reference signal should be referred to this AGND voltage. All AGND pins should be connected together. 5, 6 AVDD Analog Power Supply Input. The AVDD range for the AD7908/AD7918/AD7928 is from 2.7 V to 5.25 V. For the 0 V to 2 × REFIN range, AVDD should be from 4.75 V to 5.25 V. 7 REFIN Reference Input for the AD7908/AD7918/AD7928. An external reference must be applied to this input. The voltage range for the external reference is 2.5 V ± 1% for specified performance. 16 to 9 VIN0 to VIN7 Analog Input 0 through Analog Input 7. These are eight single-ended analog input channels that are multiplexed into the on-chip track-and-hold. The analog input channel to be converted is selected by using Address Bit ADD2 through Address Bit ADD0 of the control register. The address bits, in conjunction with the SEQ and SHADOW bits, allow the sequencer to be programmed. The input range for all input channels can extend from 0 V to REFIN or 0 V to 2 × REFIN as selected via the RANGE bit in the control register. Any unused input channels must be connected to AGND to avoid noise pickup. 18 DOUT Data Out. Logic output. The conversion result from the AD7908/AD7918/AD7928 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7908 consists of one leading zero, three address bits indicating which channel the conversion result corresponds to, followed by the eight bits of conversion data, followed by four trailing zeros, provided MSB first; the data stream from the AD7918 consists of one leading zero, three address bits indicating which channel the conversion result corresponds to, followed by the 10 bits of conversion data, followed by two trailing zeros, also provided MSB first; the data stream from the AD7928 consists of one leading zero, three address bits indicating which channel the conversion result corresponds to, followed by the 12 bits of conversion data, provided MSB first. The output coding can be selected as straight binary or twos complement via the CODING bit in the control register. 19 VDRIVE Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the serial interface of the AD7908/AD7918/AD7928 operates. |
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