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ADSP-21161NKCA-100 Datasheet(PDF) 1 Page - Analog Devices |
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ADSP-21161NKCA-100 Datasheet(HTML) 1 Page - Analog Devices |
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1 / 60 page  SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc. SHARC Processor ADSP-21161N Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com SUMMARY High performance 32-Bit DSP—applications in audio, medi- cal, military, wireless communications, graphics, imaging, motor-control, and telephony Super Harvard Architecture—four independent buses for dual data fetch, instruction fetch, and nonintrusive zero- overhead I/O Code compatible with all other sharc family DSPs Single-instruction multiple-data (SIMD) computational archi- tecture—two 32-bit IEEE floating-point computation units, each with a multiplier, ALU, shifter, and register file Serial ports offer I 2S support via 8 programmable and simul- taneous receive or transmit pins, which support up to 16 transmit or 16 receive channels of audio Integrated peripherals—integrated I/O processor, 1M bit on- chip dual-ported SRAM, SDRAM controller, glueless multi- processing features, and I/O ports (serial, link, external bus, SPI, and JTAG) ADSP-21161N supports 32-bit fixed, 32-bit float, and 40-bit floating-point formats 100 MHz/110 MHz core instruction rate Single-cycle instruction execution, including SIMD opera- tions in both computational units Up to 660 MFLOPs peak and 440 MFLOPs sustained performance 225-ball 17 mm 17 mm CSP_BGA package Figure 1. ADSP-21161N Functional Block Diagram ALU MULT DATA REGISTER FILE (PEY) 16 40-BIT BARREL SHIFTER BARREL SHIFTER ALU DATA REGISTER FILE (PEX) 16 40-BIT TIMER INSTRUCTION CACHE 32 48-BIT DAG1 8 4 32 PROGRAM SEQUENCER 32 PM ADDRESS BUS DM ADDRESS BUS 32 BUS CONNECT (PX) PM DATA BUS DM DATA BUS 64 64 CORE PROCESSOR SPI PORTS (1) SERIAL PORTS (4) LINK PORTS (2) DMA CONTROLLER 5 16 20 4 IOP REGISTERS (MEMORY MAPPED) CONTROL, STATUS, & DATA BUFFERS I/O PROCESSOR TWO INDEPENDENT DUAL-PORTED BLOCKS ADDR DATA DATA DATA ADDR ADDR DATA ADDR PROCESSOR PORT I/O PORT DUAL-PORTED SRAM HOST PORT ADDR BUS MUX MULTIPROCESSOR INTERFACE DATA BUS MUX 32 24 EXTERNAL PORT 6 12 8 JTAG TEST AND EMULATION GPIO FLAGS SDRAM CONTROLLER IOA 18 IOD 64 DAG2 8 4 32 MULT S |
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