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BQ76PL536A-Q1 Datasheet(PDF) 8 Page - Texas Instruments |
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BQ76PL536A-Q1 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 60 page  bq76PL536A-Q1 SLUSAM3 – MAY 2011 www.ti.com HOST INTERFACE Typical values stated where TA = 25°C and VBAT = 20 V, Min/Max values stated where TA = –40°C to 105°C and VBAT = 7.2 V to 27 V (unless otherwise noted) PARAMETER TEST CONDITION MIN TYP MAX UNIT Logic-level output voltage, high; SDO_H, FAULT_H, VOH CL = 20 pF, IOH < 5 mA (1) 4.5 VLDOD V ALERT_H, DRDY Logic-level output voltage, low; SDO_H, FAULT_H, VOL CL = 20 pF, IOL < 5 mA (1) VSS 0.5 V ALERT_H, DRDY Logic-level input voltage, high; SCLK_H, SDI_H, CS_H, VIH 2 5.2 V CONV Logic-level input voltage, low; SCLK_H, SDI_H, CS_H, VIL VSS 0.8 V CONV CIN Input capacitance SCLK_H, SDI_H, CS_H, CONV 5 pF ILKG Input leakage current SCLK_H, SDI_H, CS_H, CONV 1 µA (1) Total simultaneous current drawn from all pins is limited by LDOD current to ≤10 mA. GENERAL PURPOSE INPUT/OUTPUT (GPIO) Typical values stated where TA = 25°C and VBAT = 20 V, Min/Max values stated where TA = –40°C to 105°C and VBAT = 7.2 V to 27 V (unless otherwise noted) PARAMETER TEST CONDITION MIN TYP MAX UNIT VIH Logic-level input voltage, high Vin ≤ VREG50 2 V VIL Logic-level input voltage, low 0.8 V VOH Output high-voltage pullup voltage Supplied by external ~100-k Ω resistor VREG50 V VOL Logic-level output voltage, low IOL = 1 mA 0.3 V CIN Input capacitance(1) 5 pF ILKG Input leakage current 1 µA CELL BALANCING CONTROL OUTPUT (CBx) Typical values stated where TA = 25°C and VBAT = 20 V, Min/Max values stated where TA = –40°C to 105°C and VBAT = 7.2 V to 27 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CBz Output impedance 1 V < VCELL < 5 V 80 100 120 k Ω VRANGE Output V VCn-1 VCn V ANALOG-TO-DIGITAL CONVERTER ADC Common Specifications Typical values stated where TA = 25°C and VBAT = 20 V, Min/Max values stated where TA = –40°C to 105°C and VBAT = 7.2 V to 27 V (unless otherwise noted) PARAMETER TEST CONDITION MIN TYP MAX UNIT ADC_CONTROL[ADC_ON] = 1 5.4 6 6.6 µs tCONV_START CONV high to conversion start(1) (2) ADC_CONTROL[ADC_ON] = 0 500 µs tCONV Conversion time per selected channel(3) ADC_CONTROL[ADC_ON] = 1 5.4 6 6.6 µs ILKG Input leakage current Not converting <10 100 nA (1) If ADC_CONTROL[ADC_ON] = 0, add 500 µs to conversion time to allow ADC subsystem to stabilize. This is self-timed by the part. (2) Additional 50 ms (POR) is required before first conversion after a) initial cell connection; or b) VBAT falls below VPOR. (3) Plus tCONV_START, i.e., if device is programmed for six channel conversions, total time is approximately 6 × 6 + 6 = 42 µs. 8 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): bq76PL536A-Q1 |
Similar Part No. - BQ76PL536A-Q1_13 |
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Similar Description - BQ76PL536A-Q1_13 |
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