DAC0830, DAC0832

SNAS534B – MAY 1999 – REVISED MARCH 2013

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Connection Diagrams

(Top Views)

Figure 1. PDIP, CDIP, and SOIC Packages

Figure 2. PLCC Package

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings

(1) (2) (3)

Voltage at Any Digital Input

±25V

Storage Temperature Range

−65°C to +150°C

Package Dissipation at

500 mW

(4)

DC Voltage Applied to

(5)

800V

Lead

PDIP Package (plastic)

260°C

Temperature

CDIP Package (ceramic)

300°C

(Soldering, 10

SOIC Package

Vapor Phase (60 sec.)

215°C

sec.)

Infrared (15 sec.)

220°C

(1)

All voltages are measured with respect to GND, unless otherwise specified.

(2)

Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not

apply when operating the device beyond its specified operating conditions.

(3)

If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.

(4)

thermal resistance of the J package when board mounted is 80°C/W. For the NFH package, this number increases to 100°C/W and for

the FN package this number is 120°C/W.

(5)

introduce an additional 0.01% linearity error.

(6)

Human body model, 100 pF discharged through a 1.5 k

Ω resistor.

2

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