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TMS320C6414T Datasheet(PDF) 84 Page - Texas Instruments |
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TMS320C6414T Datasheet(HTML) 84 Page - Texas Instruments |
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84 / 146 page  TMS320C6414T, TMS320C6415T, TMS320C6416T FIXEDPOINT DIGITAL SIGNAL PROCESSORS SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009 84 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 INPUT AND OUTPUT CLOCKS (CONTINUED) 1 5 6 2 3 ECLKIN ECLKOUT1 4 4 Figure 20. ECLKOUT1 Timing for EMIFA and EMIFB Modules switching characteristics over recommended operating conditions for ECLKOUT2 for the EMIFA and EMIFB modules†‡§ (see Figure 21) NO. PARAMETER −600 −720 −850 −1G UNIT MIN MAX 1 tJ(EKO2) Period jitter, ECLKOUT2 0 ±175¶ ps 2 tw(EKO2H) Pulse duration, ECLKOUT2 high 0.5NE − 0.7 0.5NE + 0.7 ns 3 tw(EKO2L) Pulse duration, ECLKOUT2 low 0.5NE − 0.7 0.5NE + 0.7 ns 4 tt(EKO2) Transition time, ECLKOUT2 1 ns 5 td(EKIH-EKO2H) Delay time, ECLKIN high to ECLKOUT2 high 3 8 ns 6 td(EKIH-EKO2L) Delay time, ECLKIN high to ECLKOUT2 low 3 8 ns † The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. ‡ These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted. § E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB. N = the EMIF input clock divider; N = 1, 2, or 4. ¶ This cycle-to-cycle jitter specification was measured with CPU/4 or CPU/6 as the source of the EMIF input clock. 5 6 ECLKIN ECLKOUT2 3 2 4 4 1 Figure 21. ECLKOUT2 Timing for the EMIFA and EMIFB Modules |
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