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TMS320DM8168SCYG4 Datasheet(PDF) 10 Page - Texas Instruments |
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TMS320DM8168SCYG4 Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 327 page  TMS320DM8168, TMS320DM8167 TMS320DM8166, TMS320DM8165 SPRS614D – MARCH 2011 – REVISED JANUARY 2013 www.ti.com Table 2-2. Characteristics of the Processor (continued) HARDWARE FEATURES DM8168, DM6187, DM8166 and DM6185 ADDITIONAL SHARED MEMORY 512KB On-chip RAM CPU ID + CPU Rev ID Control Status Register (CSR.[31:16]) 0x1003 C674x Megamodule Revision Revision ID Register (MM_REVID[15:0]) 0x0000 JTAG BSDL_ID JTAGID Register 0x2B81 E02F ARM Cortex-A8: 1000 MHz DM8168 - ARM: 1000; DSP: 800 DSP: 800 MHz ARM Cortex-A8: 1200 MHz DM8168 - ARM: CPU Frequency(1) MHz 1200; DSP: 1000 DSP: 1000 MHz ARM Cortex-A8: 1350 MHz DM8168 - ARM: 1350; DSP: 1125 DSP: 1125 MHz ARM Cortex-A8: 1.00 ns DM8168 - ARM: 1000; DSP: 800 DSP: 1.25 ns ARM Cortex-A8: 0.83 ns DM8168 - ARM: Cycle Time ns 1200; DSP: 1000 DSP: 1.00 ns ARM Cortex-A8: 0.74 ns DM8168 - ARM: 1350; DSP: 1125 DSP: 0.89 ns Core Logic (V) 1.0 V with Required AVS Capability USB Logic (V) 0.9 V Voltage RAM (V) 1.0 V IO (V) 1.5 V, 1.8 V, 3.3 V Package 25 x 25 mm 1031-Pin BGA (CYG) Process Technology µm 0.04 µm Product Preview (PP), Product Status(2) Advance Information (AI), PD or Production Data (PD) (1) For more information on the available device speed ranges for each part number, see Table 9-1. (2) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. 2.3 ARM Subsystem The ARM subsystem is designed to give the ARM Cortex-A8 master control of the device. In general, the ARM Cortex-A8 is responsible for configuration and control of the various subsystem, peripherals, and external memories. The ARM subsystem includes the following features: • ARM Cortex-A8 RISC processor: – ARMv7 ISA plus Thumb®-2, Jazelle-X, and media extensions – NEON floating-point unit – Enhanced memory management unit (MMU) – Little Endian – 32KB L1 instruction cache – 32KB L1 data cache – 256KB L2 cache • Foresight embedded trace module (ETM) • ARM Cortex-A8 interrupt controller (AINTC) • 64KB internal RAM • 48KB internal public ROM. 10 Device Overview Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320DM8168 TMS320DM8167 TMS320DM8166 TMS320DM8165 |
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