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TMS320F28234ZJZQ Datasheet(PDF) 10 Page - Texas Instruments |
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TMS320F28234ZJZQ Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 199 page  TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com Digital Signal Controllers (DSCs) Check for Samples: TMS320F28335, TMS320F28334, TMS320F28332, TMS320F28235, TMS320F28234, TMS320F28232 1 TMS320F2833x, TMS320F2823x DSCs 1.1 Features 123 • High-Performance Static CMOS Technology • Enhanced Control Peripherals – Up to 150 MHz (6.67-ns Cycle Time) – Up to 18 PWM Outputs – 1.9-V/1.8-V Core, 3.3-V I/O Design – Up to 6 HRPWM Outputs With 150 ps MEP Resolution • High-Performance 32-Bit CPU (TMS320C28x) – Up to 6 Event Capture Inputs – IEEE-754 Single-Precision Floating-Point Unit (FPU) (F2833x only) – Up to 2 Quadrature Encoder Interfaces – 16 x 16 and 32 x 32 MAC Operations – Up to 8 32-Bit Timers (6 for eCAPs and 2 for eQEPs) – 16 x 16 Dual MAC – Up to 9 16-Bit Timers – Harvard Bus Architecture (6 for ePWMs and 3 XINTCTRs) – Fast Interrupt Response and Processing • Three 32-Bit CPU Timers – Unified Memory Programming Model • Serial Port Peripherals – Code-Efficient (in C/C++ and Assembly) – Up to 2 CAN Modules • Six-Channel DMA Controller (for ADC, McBSP, – Up to 3 SCI (UART) Modules ePWM, XINTF, and SARAM) – Up to 2 McBSP Modules (Configurable as • 16-Bit or 32-Bit External Interface (XINTF) SPI) – Over 2M x 16 Address Reach – One SPI Module • On-Chip Memory – One Inter-Integrated-Circuit (I2C) Bus – F28335, F28235: • 12-Bit ADC, 16 Channels 256K x 16 Flash, 34K x 16 SARAM – 80-ns Conversion Rate – F28334, F28234: 128K x 16 Flash, 34K x 16 SARAM – 2 x 8 Channel Input Multiplexer – F28332, F28232: – Two Sample-and-Hold 64K x 16 Flash, 26K x 16 SARAM – Single/Simultaneous Conversions – 1K x 16 OTP ROM – Internal or External Reference • Boot ROM (8K x 16) • Up to 88 Individually Programmable, – With Software Boot Modes (via SCI, SPI, Multiplexed GPIO Pins With Input Filtering CAN, I2C, McBSP, XINTF, and Parallel I/O) • JTAG Boundary Scan Support (1) – Standard Math Tables • Advanced Emulation Features • Clock and System Control – Analysis and Breakpoint Functions – Dynamic PLL Ratio Changes Supported – Real-Time Debug via Hardware – On-Chip Oscillator • Development Support Includes – Watchdog Timer Module – ANSI C/C++ Compiler/Assembler/Linker • GPIO0 to GPIO63 Pins Can Be Connected to – Code Composer Studio™ IDE One of the Eight External Core Interrupts – DSP/BIOS™ • Peripheral Interrupt Expansion (PIE) Block That – Digital Motor Control and Digital Power Supports All 58 Peripheral Interrupts Software Libraries • 128-Bit Security Key/Lock – Protects Flash/OTP/RAM Blocks – Prevents Firmware Reverse Engineering (1) IEEE Standard 1149.1-1990 Standard Test Access Port and Boundary Scan Architecture 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 MicroStar BGA, Code Composer Studio, DSP/BIOS, TMS320C28x, Delfino, PowerPAD, TMS320C54x, TMS320C55x, C28x are trademarks of Texas Instruments. 3 All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to Copyright © 2007–2012, Texas Instruments Incorporated specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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