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FM93C86A Rev. C.1

Address

Bits(10/11)

CS

SK

DI

DO

High - Z

WRITE DISABLE CYCLE (WDS)

Start

Bit

Opcode

Bits(2)

1

0

0

A1

A0

93C86A (ORG=1;

A

Address bits pattern -> 0-0-x-x-x-x-x-x-x-x; (x -> Don ’ t Care, can be 0 or 1)

93C86A (ORG=0;

A

Address bits pattern -> 0-0-x-x-x-x-x-x-x-x-x; (x -> Don ’ t Care, can be 0 or 1)

A

n

A

n-1

Address

Bits(10/11)

Data

Bits(16/8)

CS

SK

DI

DO

High - Z

WRITE CYCLE (WRITE)

Star t

Bit

93C86A (ORG=1;

A

Address bits patter n -> A9-A8-A7-A6-A5-A4-A3-A2-A1-A0; User defined

Data bits patter n

-> D15-to-D0; User defined

93C86A (ORG=0;

A

Address bits patter n -> A10-A9-A8-A7-A6-A5-A4-A3-A2-A1-A0; User defined

Data bits patter n

-> D7-to-D0; User defined

Opcode

Bits(2)

1

0

1

A

n

A

n-1

A1

A0

D

n

D

n-1

D1

Busy

Ready

D0

Address

Bits(10/11)

Data

Bits(16/8)

CS

SK

DI

DO

High - Z

WRITE ALL CYCLE (WRALL)

Star t

Bit

Opcode

Bits(2)

1

0

0

A1

A0

D1

Busy

Ready

93C86A (ORG=1;

A

Address bits patter n -> 0-1-x-x-x-x-x-x-x-x; (x -> Don't Care, can be 0 or 1)

Data bits patter n

-> D15-to-D0; User defined

93C86A (ORG=0;

A

Address bits patter n -> 0-1-x-x-x-x-x-x-x-x-x; (x -> Don't Care, can be 0 or 1)

Data bits patter n

-> D7-to-D0; User defined

A

n

A

n-1

D

n

D

n-1

D0