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STM32F405VGT6 Datasheet(PDF) 78 Page - STMicroelectronics

Part # STM32F405VGT6
Description  ARM Cortex-M4 32b MCUFPU, 210DMIPS, up to 1MB Flash/1924KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32F405VGT6 Datasheet(HTML) 78 Page - STMicroelectronics

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Electrical characteristics
STM32F405xx, STM32F407xx
78/185
DocID022152 Rev 4
V12
Regulator ON:
1.2 V internal voltage on
VCAP_1/VCAP_2 pins
VOS bit in PWR_CR register = 0(1)
Max frequency 144MHz
1.08
1.14
1.20
V
VOS bit in PWR_CR register= 1
Max frequency 168MHz
1.20
1.26
1.32
V
Regulator OFF:
1.2 V external voltage must be
supplied from external regulator
on VCAP_1/VCAP_2 pins
Max frequency 144MHz
1.10
1.14
1.20
V
Max frequency 168MHz
1.20
1.26
1.30
V
VIN
Input voltage on RST and FT
pins(6)
2V ≤ VDD ≤ 3.6 V
–0.3
-
5.5
V
VDD ≤ 2 V
–0.3
-
5.2
Input voltage on TTa pins
–0.3
-
VDDA+
0.3
Input voltage on B pin
-
5.5
PD
Power dissipation at TA = 85 °C
for suffix 6 or TA = 105 °C for
suffix 7(7)
LQFP64
-
435
mW
LQFP100
-
465
LQFP144
-
500
LQFP176
-
526
UFBGA176
-
513
WLCSP90
-
543
TA
Ambient temperature for 6 suffix
version
Maximum power dissipation
–40
85
°C
Low power dissipation(8)
–40
105
Ambient temperature for 7 suffix
version
Maximum power dissipation
–40
105
°C
Low power dissipation(8)
–40
125
TJ
Junction temperature range
6 suffix version
–40
105
°C
7 suffix version
–40
125
1. The average expected gain in power consumption when VOS = 0 compared to VOS = 1 is around 10% for the whole
temperature range, when the system clock frequency is between 30 and 144 MHz.
2. VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of
an external power supply supervisor (refer to Section : Internal reset OFF).
3. When the ADC is used, refer to Table 67: ADC characteristics.
4. If VREF+ pin is present, it must respect the following condition: VDDA-VREF+ < 1.2 V.
5. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and
VDDA can be tolerated during power-up and power-down operation.
6. To sustain a voltage higher than VDD+0.3, the internal pull-up and pull-down resistors must be disabled.
7. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax.
8. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax.
Table 14. General operating conditions (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit


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