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MC68HC05B32 Datasheet(PDF) 11 Page - Freescale Semiconductor, Inc |
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MC68HC05B32 Datasheet(HTML) 11 Page - Freescale Semiconductor, Inc |
11 / 302 page MC68HC05B6 Rev. 4.1 Freescale iii TABLE OF CONTENTS Paragraph Number Page Number TABLE OF CONTENTS 5 PROGRAMMABLE TIMER 5.1 Counter ..............................................................................................................5–1 5.1.1 Counter register and alternate counter register ...........................................5–3 5.2 Timer control and status ....................................................................................5–4 5.2.1 Timer control register (TCR) ........................................................................5–4 5.2.2 Timer status register (TSR)..........................................................................5–6 5.3 Input capture......................................................................................................5–7 5.3.1 Input capture register 1 (ICR1) ....................................................................5–7 5.3.2 Input capture register 2 (ICR2) ....................................................................5–8 5.4 Output compare .................................................................................................5–9 5.4.1 Output compare register 1 (OCR1)..............................................................5–9 5.4.2 Output compare register 2 (OCR2)............................................................5–10 5.4.3 Software force compare .............................................................................5–11 5.5 Pulse Length Modulation (PLM) ......................................................................5–11 5.5.1 Pulse length modulation registers A and B (PLMA/PLMB) ........................5–11 5.6 Timer during STOP mode................................................................................5–12 5.7 Timer during WAIT mode.................................................................................5–12 5.8 Timer state diagrams .......................................................................................5–12 6 SERIAL COMMUNICATIONS INTERFACE 6.1 SCI two-wire system features ............................................................................6–1 6.2 SCI receiver features .........................................................................................6–3 6.3 SCI transmitter features .....................................................................................6–3 6.4 Functional description........................................................................................6–3 6.5 Data format ........................................................................................................6–5 6.6 Receiver wake-up operation ..............................................................................6–5 6.6.1 Idle line wake-up ..........................................................................................6–6 6.6.2 Address mark wake-up ................................................................................6–6 6.7 Receive data in (RDI) ........................................................................................6–6 6.8 Start bit detection...............................................................................................6–6 6.9 Transmit data out (TDO) ....................................................................................6–8 6.10 SCI synchronous transmission ..........................................................................6–9 6.11 SCI registers ....................................................................................................6–10 6.11.1 Serial communications data register (SCDR) ............................................6–10 6.11.2 Serial communications control register 1 (SCCR1) ...................................6–10 6.11.3 Serial communications control register 2 (SCCR2) ...................................6–14 6.11.4 Serial communications status register (SCSR)..........................................6–16 6.11.5 Baud rate register (BAUD) .........................................................................6–18 6.12 Baud rate selection ..........................................................................................6–19 6.13 SCI during STOP mode ...................................................................................6–21 6.14 SCI during WAIT mode....................................................................................6–21 |
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