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MCF5206e Integrated ColdFire® Microprocessor Product Brief

MOTOROLA

MCF5206e Overview

frequency, which is derived from the system clock. The programmable timer-output pin generates either an

active low-pulse or toggles the output.

1.1.10 Motorola Bus (M-Bus) Module

The M-Bus interface is a two-wire, bidirectional serial bus that exchanges data between devices and is

system and is best suited for applications that need occasional bursts of rapid communication over short

distances among several devices. Bus capacitance and the number of unique addresses limit the maximum

communication length and the number of devices that can be connected.

1.1.11 System Interface

The MCF5206e processor provides a glueless interface to 8-, 16-, and 32-bit port size SRAM, ROM, and

peripheral devices with independent programmable control of the assertion and negation of chip-selects and

write-enables. Programmable address and data-hold times can be extended for a compatible interface to

external devices and memory. The MCF5206e also supports bursting ROMs.

1.1.11.1 External Bus Interface

The bus interface controller transfers information between the ColdFire core and memory, peripherals, or

other masters on the external bus. The external bus interface provides as much as 28 bits of address bus

space, a 32-bit data bus, and all associated control signals. This interface implements an extended

synchronous protocol that supports bursting operations. For nonsynchronous external memory and

peripherals, the MCF5206e processor provides an alternate asynchronous bus transfer acknowledgment

signal.

Simple two-wire request/acknowledge bus arbitration between the MCF5206e processor and another bus

master, such as the DMA device, is glueless with arbitration handled internal to the MCF5206e processor.

Alternately, an external bus arbiter can control more complex three-wire (request, grant, busy)

multiple-master bus arbitration, allowing overlapped bus arbitration with one clock-bus handovers.

1.1.11.2 Chip Selects

Eight programmable chip select outputs provide signals that enable external memory and peripheral circuits

for automatic wait-state insertion. These signals also interface to 8-, 16-, 32-bit ports. In addition, other

external bus masters can access chip selects. The other four chip-selects are multiplexed with A[27:24] of

the address bus and four write-enable signals. The base address, access permissions, and timing waveforms

are all programmable using configuration registers.

Except for fast page mode, all operations are available to other external bus masters. The DRAM controller

can generate RAS and CAS for an external master and can continue to generate refresh requests.

1.1.11.3 8-Bit Parallel Port Interface

An 8-bit general-purpose programmable parallel port serves as either an input or output on a bit-by-bit basis.

The parallel port is multiplexed with the PST[3:0] and DDATA[3:0] debug signals.

Freescale Semiconductor, Inc.

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