FM25V05 - 512Kb SPI FRAM

Document Number: 001-84497 Rev. **

Page 2 of 17

Instruction Decode

Clock Generator

Control Logic

Write Protect

Instruction Register

Address Register

Counter

8192 x 64

FRAM Array

16

Data I/O Register

8

Nonvolatile Status

Register

3

W

S

C

Q

D

HOLD

Figure 1. Block Diagram

Pin Descriptions

Pin Name

I/O

Description

/S

Input

Chip Select: This active-low input activates the device. When high, the device enters

low-power standby mode, ignores other inputs, and all outputs are tri-stated. When

low, the device internally activates the C signal. A falling edge on /S must occur prior

to every op-code.

C

Input

Serial Clock: All I/O activity is synchronized to the serial clock. Inputs are latched on

the rising edge and outputs occur on the falling edge. Since the device is static, the

clock frequency may be any value between 0 and 40 MHz and may be interrupted at

any time.

/HOLD

Input

Hold: The /HOLD pin is used when the host CPU must interrupt a memory operation

for another task. When /HOLD is low, the current operation is suspended. The device

ignores any transition on C or /S. All transitions on /HOLD must occur while C is low.

/W

Input

Write Protect: This active-low pin prevents write operations to the Status Register

only. A complete explanation of write protection is provided on pages 6 and 7. If not

D

Input

Serial Input: All data is input to the device on this pin. The pin is sampled on the

rising edge of C and is ignored at other times. It should always be driven to a valid

* D may be connected to Q for a single pin data interface.

Q

Output

Serial Output: This is the data output pin. It is driven during a read and remains tri-

stated at all other times including when /HOLD is low. Data transitions are driven on

the falling edge of the serial clock.

* Q may be connected to D for a single pin data interface.

VDD

Supply

Power Supply

VSS

Supply

Ground