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QGE7520MC-SL8EE Datasheet(PDF) 5 Page - Intel Corporation |
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QGE7520MC-SL8EE Datasheet(HTML) 5 Page - Intel Corporation |
5 / 282 page Intel® E7520 Memory Controller Hub (MCH) Datasheet 5 3.6.22 SYSBUS_NERR – System Bus Next Error Register (D0:F1)..............................88 3.6.23 SYSBUS_ERRMASK – System Bus Error Mask Register (D0:F1) .....................88 3.6.24 SYSBUS_SCICMD – System Bus SCI Command Register (D0:F1)...................89 3.6.25 SYSBUS_SMICMD – System Bus SMI Command Register (D0:F1)..................90 3.6.26 SYSBUS_SERRCMD – System Bus SERR Command Register (D0:F1) ................................................................................................................91 3.6.27 SYSBUS_MCERRCMD – System Bus MCERR# Command Register (D0:F1) ..................................................................................................92 3.6.28 BUF_FERR – Memory Buffer First Error Register (D0:F1)..................................94 3.6.29 BUF_NERR – Memory Buffer Next Error Register (D0:F1).................................94 3.6.30 BUF_ERRMASK – Memory Buffer Error Mask Register (D0:F1) ........................95 3.6.31 BUF_SCICMD – Memory Buffer SCI Command Register (D0:F1)......................96 3.6.32 BUF_SMICMD – Memory Buffer SMI Command Register (D0:F1).....................96 3.6.33 BUF_SERRCMD – Memory Buffer SERR Command Register (D0:F1) ................................................................................................................97 3.6.34 BUF_MCERRCMD – Memory Buffer MCERR# Command Register (D0:F1) ................................................................................................................98 3.6.35 DRAM_FERR – DRAM First Error Register (D0:F1) ...........................................99 3.6.36 DRAM_NERR – DRAM Next Error Register (D0:F1) ........................................101 3.6.37 DRAM_ERRMASK – DRAM Error Mask Register (D0:F1)................................101 3.6.38 DRAM_SCICMD – DRAM SCI Command Register (D0:F1) .............................102 3.6.39 DRAM_SMICMD – DRAM SMI Command Register (D0:F1) ............................103 3.6.40 DRAM_SERRCMD – DRAM SERR Command Register (D0:F1) .....................104 3.6.41 DRAM_MCERRCMD – DRAM MCERR# Command Register (D0:F1) ..............................................................................................................105 3.6.42 THRESH_SEC0 – DIMM0 SEC Threshold Register (D0:F1) ............................106 3.6.43 THRESH_SEC1 – DIMM1 SEC Threshold Register (D0:F1) ............................106 3.6.44 THRESH_SEC2 – DIMM2 SEC Threshold Register (D0:F1) ............................106 3.6.45 THRESH_SEC3 – DIMM3 SEC Threshold Register (D0:F1) ............................107 3.6.46 DRAM_SEC1_ADD – DRAM First Single-Bit Error Correct Address Register (D0:F1) ..................................................................................107 3.6.47 DRAM_DED_ADD – DRAM DED Error Address (D0:F1) .................................108 3.6.48 DRAM_SCRB_ADD – DRAM Scrub Error Address Register (D0:F1) ..............................................................................................................108 3.6.49 DRAM_RETR_ADD – DRAM DED Retry Address (D0:F1)...............................109 3.6.50 DRAM_SEC_D0A – DRAM DIMM0 Channel A SEC Counter Register (D0:F1) ................................................................................................109 3.6.51 DRAM_DED_D0A – DRAM DIMM0 Channel A DED Counter Register (D0:F1) ................................................................................................110 3.6.52 DRAM_SEC_D1A – DRAM DIMM1 Channel A SEC Counter Register (D0:F1) ................................................................................................110 3.6.53 DRAM_DED_D1A – DRAM DIMM1 Channel A DED Counter Register (D0:F1) ................................................................................................111 3.6.54 DRAM_SEC_D2A – DRAM DIMM2 Channel A SEC Counter Register (D0:F1) ................................................................................................111 3.6.55 DRAM_DED_D2A – DRAM DIMM2 Channel A DED Counter Register (D0:F1) ................................................................................................111 3.6.56 DRAM_SEC_D3A – DRAM DIMM3 Channel A SEC Counter Register (D0:F1) ................................................................................................112 3.6.57 DRAM_DED_D3A – DRAM DIMM3 Channel A DED Counter Register (D0:F1) ................................................................................................112 3.6.58 THRESH_DED – DED Threshold Register (D0:F1) ..........................................112 3.6.59 DRAM_SEC2_ADD – DRAM Next Single-Bit Error Correct Address Register (D0:F1) ..................................................................................113 3.6.60 DRAM_SEC_D0B – DRAM DIMM0 Channel B SEC Counter Register (D0:F1) ................................................................................................113 |
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