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Z86E4016PSG Datasheet(PDF) 10 Page - Zilog, Inc. |
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Z86E4016PSG Datasheet(HTML) 10 Page - Zilog, Inc. |
10 / 64 page PS011706-0511 Overview CMOS SCC Serial Communications Controller Product Specification 2 • New programmable WR7 (Write register 7 prime) to enable new features • Improvements to support SDLC mode of synchronous communication: – Improve functionality to ease sending back-to-back frames – Automatic SDLC opening Flag transmission – Automatic Tx Underrun/EOM Latch reset in SDLC mode – Automatic RTS deactivation – TxD pin forced High in SDLC NRZI mode after closing flag – Complete CRC reception – Improved response to Abort sequence in status FIFO – Automatic Tx CRC generator preset/reset – Extended Read for Write registers – Write data set-up timing improvement • Improved AC timing: – 3 to 3.6 PCLK access recovery time – Programmable DTR/REQ timing – Write data to falling edge of WR setup time requirement is now eliminated – Reduced INT timing • Other features include: – Extended Read function to read back the written value to the Write registers – Latching RRO during read – RRO, bit D7 and RR10, bit D6 now has reset default value |
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