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AD5360BSTZ1 Datasheet(PDF) 6 Page - Analog Devices |
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AD5360BSTZ1 Datasheet(HTML) 6 Page - Analog Devices |
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6 / 28 page  AD5360/AD5361 Rev. A | Page 6 of 28 TIMING CHARACTERISTICS DVCC = 2.5 V to 5.5 V; VDD = 9 V to 16.5 V; VSS = −8 V to −16.5 V; VREF = 5 V; AGND = DGND = SIGGND = 0 V; CL = 200 pF to GND; RL = open circuit; gain (M), offset (C), and DAC offset registers at default values; all specifications TMIN to TMAX, unless otherwise noted. Table 3. SPI Interface (See Figure 4 and Figure 5) Parameter1, 2 Limit at TMIN, TMAX Unit Description t1 20 ns min SCLK cycle time t2 8 ns min SCLK high time t3 8 ns min SCLK low time t4 11 ns min SYNC falling edge to SCLK falling edge setup time t5 20 ns min Minimum SYNC high time t6 10 ns min 24th SCLK falling edge to SYNC rising edge t7 5 ns min Data setup time t8 5 ns min Data hold time t93 42 ns max SYNC rising edge to BUSY falling edge t10 1/1.5 μs typ/max BUSY pulse width low (single-channel update); see Table 8 t11 600 ns max Single-channel update cycle time t12 20 ns min SYNC rising edge to LDAC falling edge t13 10 ns min LDAC pulse width low t14 3 μs max BUSY rising edge to DAC output response time t15 0 ns min BUSY rising edge to LDAC falling edge t16 3 μs max LDAC falling edge to DAC output response time t17 20/30 μs typ/max DAC output settling time t18 140 ns max CLR/RESET pulse activation time t19 30 ns min RESET pulse width low t20 400 μs max RESET time indicated by BUSY low t21 270 ns min Minimum SYNC high time in readback mode t224 25 ns max SCLK rising edge to SDO valid t23 80 ns max RESET rising edge to BUSY falling edge 1 Guaranteed by design and characterization, not production tested. 2 All input signals are specified with tr = tf = 2 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V. 3 This is measured with the load circuit shown in Figure 2. 4 This is measured with the load circuit shown in Figure 3. TO OUTPUT PIN CL 50pF RL 2.2kΩ VOL DVCC VOH (MIN) – VOL (MAX) 2 200µA IOL 200µA IOH TO OUTPUT PIN CL 50pF Figure 2. Load Circuit for BUSY Timing Diagram Figure 3. Load Circuit for SDO Timing Diagram |
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