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AD5553CRMZ Datasheet(PDF) 1 Page - Analog Devices |
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AD5553CRMZ Datasheet(HTML) 1 Page - Analog Devices |
1 / 20 page Current Output/Serial Input, 16-/14-Bit DACs Data Sheet AD5543/AD5553 Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2002–2012 Analog Devices, Inc. All rights reserved. FEATURES 16-bit resolution AD5543 14-bit resolution AD5553 ±1 LSB DNL ±1 LSB INL Low noise: 12 nV/√Hz Low power: IDD = 10 µA 0.5 µs settling time 4Q multiplying reference input 2 mA full-scale current ± 20%, with VREF = 10 V Built-in RFB facilitates voltage conversion 3-wire interface Ultracompact 8-lead MSOP and 8-lead SOIC packages APPLICATIONS Automatic test equipment Instrumentation Digitally controlled calibration Industrial control PLCs GENERAL DESCRIPTION The AD5543/AD5553 are precision 16-/14-bit, low power, current output, small form factor digital-to-analog converters (DACs). They are designed to operate from a single 5 V supply with a ±10 V multiplying reference. The applied external reference, VREF, determines the full-scale output current. An internal feedback resistor (RFB) facilitates the R-2R and temperature tracking for voltage conversion when combined with an external op amp. A serial-data interface offers high speed, 3-wire microcontroller- compatible inputs using serial data in (SDI), clock (CLK), and chip select (CS). The AD5543/AD5553 are packaged in ultracompact (3 mm × 4.7 mm) 8-lead MSOP and 8-lead SOIC packages. FUNCTIONAL BLOCK DIAGRAM 16-BIT/14-BIT SHIFT REGISTER DAC REGISTER AD5543/AD5553 DAC VDD VREF RFB IOUT CS CLK SDI GND CONTROL LOGIC 16 OR 14 16 OR 14 Figure 1. CODE 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 Figure 2. Integral Nonlinearity 2 0 –2 –4 –6 –8 –10 –12 –14 10k 100k 1M 10M 100M FREQUENCY (Hz) Figure 3. Reference Multiplying Bandwidth |
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