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TLV5625CDR Datasheet(PDF) 11 Page - Texas Instruments |
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TLV5625CDR Datasheet(HTML) 11 Page - Texas Instruments |
11 / 15 page TLV5625 2.7V TO 5.5V LOW POWER DUAL 8BIT DIGITALTOANALOG CONVERTER WITH POWER DOWN SLAS233D − JULY 1999 − REVISED JULY 2002 11 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 APPLICATION INFORMATION data format The 16-bit data word for the TLV5625 consists of two parts: D Program bits (D15..D12) D New data (D11..D4) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 R1 SPD PWR R0 MSB 8 Data bits LSB 0 0 0 0 SPD: Speed control bit 1 → fast mode 0 → slow mode PWR: Power control bit 1 → power down 0 → normal operation On power up, SPD and PWD are reset to 0 (slow mode and normal operation) The following table lists all possible combination of register-select bits: register-select bits R1 R0 REGISTER 0 0 Write data to DAC B and BUFFER 0 1 Write data to BUFFER 1 0 Write data to DAC A and update DAC B with BUFFER content 1 1 Reserved The meaning of the 12 data bits depends on the register. If one of the DAC registers or the BUFFER is selected, then the 12 data bits determine the new DAC value: examples of operation D Set DAC A output, select fast mode: Write new DAC A value and update DAC A output: D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 0 New DAC A output value 0 0 0 0 The DAC A output is updated on the rising clock edge after D0 is sampled. D Set DAC B output, select fast mode: Write new DAC B value to BUFFER and update DAC B output: D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 New BUFFER content and DAC B output value 0 0 0 0 The DAC A output is updated on the rising clock edge after D0 is sampled. D Set DAC A value, set DAC B value, update both simultaneously, select slow mode: 1. Write data for DAC B to BUFFER: D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 New DAC B value 0 0 0 0 2. Write new DAC A value and update DAC A and B simultaneously: D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 New DAC A value 0 0 0 0 |
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