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IR5001STRPBF Datasheet(PDF) 3 Page - International Rectifier |
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IR5001STRPBF Datasheet(HTML) 3 Page - International Rectifier |
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3 / 12 page  IR5001S & (PbF) 3 www.irf.com PIN DESCRIPTIONS Note 1: Guaranteed by design but not tested in production. Note 2: Low Vcc output voltage corresponds to low UVLO voltage PIN# PIN SYMBOL PIN DESCRIPTION 1 Vline IC power supply pin for 36V to 75V input communications systems. Minimum 25V has to be applied at this pin to bias the IC. 2Vcc Output pin of the internal shunt regulator, or input pin for biasing the IC via external resistor. This pin is internally regulated at 12.5V typical. A minimum 0.1uF capacitor must be connected from this pin to Gnd of IR5001. 3FETch FET check input pin. Together with FET status output pin, the FETch pin can be used to determine the state of the Active ORing circuit and power system redundancy. 4FETst FET status output pin. Together with FETch input pin, the FETst pin can be used to determine the state of the Active ORing circuit and power system redundancy. 5INP Positive input of internal comparator. This pin should connect to the source of N-channel Active ORing MOSFET. 6INN Negative input pin of internal comparator. This pin should connect to the drain of N-channel Active ORing MOSFET. 7 Gnd Ground pin of the IR5001. 8 Vout Output pin for the IR5001. This pin is used to directly drive the gate of the Active Oring N-Channel MOSFET. PARAMETERS SYMBOL TEST CONDITION MIN TYP MAX UNITS Output Section High Level Output Voltage Vout HI Vline=25V, IOH=50uA, V(INN)=-0.3V 10.2 11.5 14.1 V Low Level Output Voltage Vout LO IOL=100mA, V(INN)=+0.3V 0.1 V Turn-On DelayTime td(on) 5 27 45 us Rise Time tr 0.09 0.7 1 ms Turn-Off Delay Time td(off) 110 130 170 Fall Time tf 10 26 39 FETch and FETst FETch Sink Current I(FETch) FETch=5V -0.5 -1.1 -2 uA FETch Output Delay Time FETch_pd Note 1 0.8 1.8 us FETch Threshold Vth(FETch) 0.9 1.2 1.5 V FETst Threshold Voltage Vth(FETst) 5k resistor from FETst to 5V logic bias. V(INP) = Gnd, V(INN) ramping down from 0 until FETst switches to Low. -525 -300 -200 mV FETst Low Level Output Voltage VOL Isink=1mA, V(INN)=-0.5V 0 50 100 mV Vout switching from LO to HI, Fig.5 Vout switching from HI to LO, Fig.5 ns |
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