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IR5001STRPBF Datasheet(PDF) 9 Page - International Rectifier |
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IR5001STRPBF Datasheet(HTML) 9 Page - International Rectifier |
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9 / 12 page  IR5001S & (PbF) 9 www.irf.com guarantees that once the ORing N-FET is conducting and Vout of the IR5001S is high (FET current flows from source to drain), the current must reverse the direction before the IR5001S will switch the FET off. The asymmetrical offset voltage prevents potential oscillations at light load that could otherwise occur if the offset voltage was centered around 0mV (as is the case in standard comparators). Vout Vout is the output pin of the IR5001S, and connects directly to the gate of the external Active ORing N- FET. The voltage level at the Vout pin is typically a diode drop lower than the Vcc voltage. FETst and FETch FETch and FETst pins are diagnostic pins that can be used to determine the status of the Active ORing circuit. FETst is an open-drain output pin. When the voltage difference between VINP - VINN is less than 0.3V, the FETst pin will be logic high. This is normally the case when Active ORing is operating properly (VINP - VINN is less than ~100mV). If the Active ORing FET is not turned on while the IR5001S is properly biased, the output of the FETst pin will be logic low (only the body diode of the N-FET is conducting, and VINP - VINN is ~700mV). FETch pin. In traditional systems with diode ORing, it is not possible to determine if the diode is functioning properly unless external circuitry is used. For example, the diode could be failed short, and the system would not be aware of it until the source fails and the whole system gets powered down due to lost redundancy (shorted diode failed to isolate the source failure). With the FETch pin it is possible to perform a periodic check of the status of the Active ORing circuit to assure that system redundancy is maintained. In the IR5001S, the FETch pin is an input pin that can be used to turn off the output of the IR5001S: logic high signal on FETch will pull the Vout pin low, and turn-off the channel of the Active ORing N-FET. This will force the current to flow through the body diode, resulting in VINP – VINN voltage increase from less than ~100mV, to ~700mV. This voltage increase will be reported at FETst pin, which will switch from logic high to logic low, and indicate that the Active ORing circuit is working properly. Failure of the FETst pin output to change from logic high to logic low would indicate that the Active ORing circuit may not be operating as designed, and the system may no longer have power redundancy. For details on how to use this feature consult IR5001S Evaluation Kit, P/N IRDC5001-LS48V. If the FETch pin is not used, it should be tied to ground (for noise immunity purposes). FETst pin should be left open if unused. Gnd In typical target applications, the ground pin (Gnd) of IR5001S is connected to the source of the Active ORing N-FET. |
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