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HCPL-5731 Datasheet(PDF) 11 Page - AVAGO TECHNOLOGIES LIMITED |
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HCPL-5731 Datasheet(HTML) 11 Page - AVAGO TECHNOLOGIES LIMITED |
11 / 12 page 11 Figure 8. Switching Test Circuit (f, tP not JEDEC registered). Figure 9. Test Circuit for Transient Immunity and Typical Waveforms. Figure 10. Recommended Drive Circuitry Using TTL Open-Collector Logic. IF RL RCC* 56 1.0 F +5 V VO * SEE NOTE 11 Rm IF MONITOR PULSE GEN. ZO = 50 tr, tf = 50 ns f = 100 Hz tPULSE = 0.5ms CL** ** CL INCLUDES PROBE AND STRAY WIRING CAPACITANCE. 7 5 6 8 2 3 4 1 VFF IF VCM RL RCC* 56 1.0 F +5 V VO + – PULSE GEN. * SEE NOTE 11 A B 7 5 6 8 2 3 4 1 ILEAK R2 MAY BE OMITTED IF ADDITIONAL FANOUT IS NOT USED. R1 R2 VCC R2 ≥ 2.4 VF IF 7 5 6 8 2 3 4 1 R1 ≤ VCC VF IF R2 IF + ILEAK |
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