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ADS62P19 Datasheet(PDF) 9 Page - Texas Instruments |
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ADS62P19 Datasheet(HTML) 9 Page - Texas Instruments |
9 / 65 page Dn_Dn+1_P DAnP/DBnP Dn_Dn+1_M DAnM/DBnM GND GND V V OCM Logic0 V = –350mV ODL (1) Logic1 V =350mV ODH (1) T0334-02 V pp V p 0 V - V CLKP CLKM ADS62P19 www.ti.com SLAS937 – APRIL 2013 Table 4. CMOS Timings at Lower Sampling Frequencies with Respect to CLKOUT TIMINGS SPECIFIED WITH RESPECT TO CLKOUT SAMPLING FREQUENCY (MSPS) SETUP TIME (ns) HOLD TIME (ns) tPDI (ns) MIN TYP MAX MIN TYP MAX MIN TYP MAX 170 2.1 3.7 0.35 1.0 7.1 8.6 10.1 150 2.8 4.4 0.5 1.2 7.4 8.9 10.4 125 3.8 5.4 0.8 1.5 7.7 9.2 10.7 < 80 5 1.2 (enable low-speed mode for fS ≤ 80) (1) 1 ≤ fS ≤ 80 9 (enable low-speed mode for fS ≤ 80) (1) (1) Low-speed mode can only be enabled with the serial interface configuration. PARAMETRIC MEASUREMENT INFORMATION TIMING DIAGRAMS Figure 1. Clock Amplitude Definition Diagram (1) With external 100- Ω termination Figure 2. LVDS Output Voltage Levels Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: ADS62P19 |
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