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ADS62P29 Datasheet(PDF) 5 Page - Texas Instruments |
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ADS62P29 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 65 page  ADS62P19 www.ti.com SLAS937 – APRIL 2013 ELECTRICAL CHARACTERISTICS: ADS62P19 Typical values are at TA = +25°C, AVDD = 3.3 V, DRVDD = 1.8 V, 50% clock duty cycle, –1-dBFS differential analog input, 0-dB gain, and internal reference mode, unless otherwise noted. Minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = +85°C, AVDD = 3.3 V, and DRVDD = 1.8 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fIN = 20 MHz 66.5 dBFS fIN = 60 MHz 66.4 dBFS fIN = 100 MHz 66.1 dBFS SNR Signal to noise ratio, LVDS 0-dB gain 64.5 65.9 dBFS fIN = 170 MHz 6-dB gain 64.1 dBFS fIN = 230 MHz 65.4 dBFS fIN = 20 MHz 66.5 dBFS fIN = 60 MHz 66.3 dBFS fIN = 100 MHz 65.9 dBFS Signal to noise and distortion ratio, SINAD LVDS 0-dB gain 63.5 65.3 dBFS fIN = 170 MHz 6-dB gain 64 dBFS fIN = 230 MHz 65.2 dBFS ENOB Effective number of bits fIN = 170 MHz 10.6 LSB DNL Differential nonlinearity fIN = 170 MHz –0.6 ±0.1 LSB INL Integrated nonlinearity fIN = 170 MHz ±0.5 ±2.5 LSB fIN = 20 MHz 89 dBc fIN = 60 MHz 85 dBc Spurious-free dynamic range fIN = 100 MHz 78 dBc fIN = 170 MHz 69.5 75 dBc fIN = 230 MHz 77 dBc SFDR fIN = 20 MHz 98 dBc fIN = 60 MHz 95 dBc Spurious-free dynamic range fIN = 100 MHz 88 dBc (excluding HD2, HD3) fIN = 170 MHz 75 88 dBc fIN = 230 MHz 87 dBc fIN = 20 MHz 93 dBc fIN = 60 MHz 90 dBc HD2 Second-order harmonic distortion fIN = 100 MHz 90 dBc fIN = 170 MHz 69.5 85 dBc fIN = 230 MHz 85 dBc fIN = 20 MHz 89 dBc fIN = 60 MHz 85 dBc HD3 Third-order harmonic distortion fIN = 100 MHz 78 dBc fIN = 170 MHz 69.5 75 dBc fIN = 230 MHz 77 dBc fIN = 20 MHz 87 dBc fIN = 60 MHz 83.5 dBc THD Total harmonic distortion fIN = 100 MHz 77.5 dBc fIN = 170 MHz 68 74 dBc fIN = 230 MHz 75 dBc f1 = 46 MHz, f2 = 50 MHz, each tone at –7 dBFS 87 dBFS IMD Two-tone intermodulation distortion f1 = 185 MHz, f2 = 190 MHz, each tone at –7 dBFS 85 dBFS Crosstalk Up to 200-MHz crosstalk frequency 90 dB Recovery to within 1% (of final value) for 6-dB overload Clock Input overload recovery 1 with sine-wave input cycles PSRR AC power-supply rejection ratio For 100-mVPP signal on AVDD supply 25 dB Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: ADS62P19 |
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