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ADS62P48 Datasheet(PDF) 4 Page - Texas Instruments |
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ADS62P48 Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 65 page  ADS62P19 SLAS937 – APRIL 2013 www.ti.com ELECTRICAL CHARACTERISTICS: GENERAL Typical values are at TA = +25°C, AVDD = 3.3 V, DRVDD = 1.8 V, 50% clock duty cycle, –1-dBFS differential analog input, and internal reference mode, unless otherwise noted. Minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = +85°C, AVDD = 3.3 V, and DRVDD = 1.8 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT VID Differential input voltage range 0-dB gain 2 VPP Differential input resistance At dc, see Figure 45 > 1 M Ω Differential input capacitance See Figure 46 3.5 pF Analog input bandwidth With 25- Ω source impedance 700 MHz Analog input common-mode Per channel 3.6 μA/MSPS current VCM Common-mode output voltage 1.5 V VCM Output current capability ±4 mA DC ACCURACY EO Offset error –20 ±2 20 mV Temperature coefficient of offset 0.02 mV/°C error Variation of offset error with 0.5 mV/V supply Two sources of gain error: internal reference inaccuracy and channel gain error Gain error resulting from internal EGREF –1 ±0.2 1 % FS reference inaccuracy alone EGCHAN Gain error of channel alone(1) –1 ±0.2 1 % FS Temperature coefficient of 0.002 Δ%/°C EGCHAN Difference in gain errors between two –2 2 %FS channels within the same device Gain matching(2) Difference in gain errors between two –4 4 %FS channels across two devices POWER SUPPLY IAVDD Analog supply current 305 350 mA LVDS interface with 100- Ω external 133 175 mA termination IDRVDD Output buffer supply current CMOS interface, fIN = 2 MHz, fS = 210 MSPS, 91 mA no external load capacitance(3)(4) AVDD Analog power 1.01 1.15 W DVDD Digital power LVDS interface 0.24 0.315 W Global power down 45 100 mW (1) This parameter is specified by design and characterization; not tested in production. (2) For two channels within the same device, only the channel gain error matters because the reference is common for both channels. (3) In CMOS mode, the DRVDD current scales with the sampling frequency, the load capacitance on output pins, input frequency, and the supply voltage (see Figure 31 and the CMOS Interface Power Dissipation section in the Application Information). (4) The maximum DRVDD current with CMOS interface depends on the actual load capacitance on the digital output lines. Note that the maximum recommended load capacitance on each digital output line is 10 pF. 4 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS62P19 |
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