 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ADS62P19IRGCR Datasheet(PDF) 7 Page - Texas Instruments |
|
|
||||||||||||||||||||||||||||||
ADS62P19IRGCR Datasheet(HTML) 7 Page - Texas Instruments |
|
|
7 / 65 page  ADS62P19 www.ti.com SLAS937 – APRIL 2013 TIMING REQUIREMENTS: LVDS AND CMOS MODES (1) Typical values are at TA = +25°C, AVDD = 3.3 V, DRVDD = 1.8 V, sampling frequency = 250 MSPS, sine-wave input clock, 1.5-VPP clock amplitude, CLOAD = 5 pF (2), and R LOAD = 100 Ω (3), unless otherwise noted. Minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = +85°C, AVDD = 3.3 V, and DRVDD = 1.7 V to 1.9 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ta Aperture delay 0.7 1.2 1.7 ns Aperture delay matching Between two channels within the same device ±50 ps tj Aperture jitter 145 fS RMS Time to valid data after exiting STANDBY mode 1 3 μs Time to valid data after exiting global power-down 20 50 μs Wake-up time 10 Clock Time to valid data after stopping and restarting the input clock cycles Clock ADC latency(4) 22 cycles DDR LVDS MODE(5) tsu Data setup time Data valid(6) to CLKOUTP zero-crossing 0.55 0.9 ns th Data hold time CLKOUTP zero-crossing to data becoming invalid(6) 0.55 0.95 ns tPDI Input clock falling edge crossover to output clock rising edge tPDI = 0.69 × tS + tdelay crossover Clock propagation delay 100 MSPS ≤ sampling frequency ≤ 250 MSPS tdelay 4.2 5.7 7.2 ns tS = 1 / sampling frequency Difference in tdelay between two devices operating at same tdelay skew ±500 ps temperature and DRVDD supply voltage Differential clock duty cycle (CLKOUTP – CLKOUTM) LVDS bit clock duty cycle 52% 100 MSPS ≤ sampling frequency ≤ 250 MSPS Rise time measured from –100 mV to +100 mV tRISE, Data rise time, Fall time measured from +100 mV to –100 mV 0.14 ns tFALL Data fall time 1 MSPS ≤ sampling frequency ≤ 250 MSPS Rise time measured from –100 mV to +10 0mV tCLKRISE, Output clock rise time, Fall time measured from +100 mV to –100 mV 0.14 ns tCLKFALL Output clock fall time 1 MSPS ≤ sampling frequency ≤ 250 MSPS Output buffer enable to tOE Time to valid data after output buffer becomes active 100 ns data delay (1) Timing parameters are ensured by design and characterization and are not tested in production. (2) CLOAD is the effective external single-ended load capacitance between each output pin and ground. (3) RLOAD is the differential load resistance between the LVDS output pair. (4) At higher clock frequencies, tPDI is greater than one clock period and overall latency = ADC latency + 1. (5) Measurements are done with a transmission line of 100- Ω characteristic impedance between the device and load. Setup and hold time specifications take into account the effect of jitter on the output data and clock. (6) Data valid refers to a logic high of +100.0 mV and a logic low of –100.0 mV. Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: ADS62P19 |
Similar Part No. - ADS62P19IRGCR |
|
Similar Description - ADS62P19IRGCR |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
