 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
TPS2483PWR Datasheet(PDF) 10 Page - Texas Instruments |
|
|
||||||||||||||||||||||||||||||
TPS2483PWR Datasheet(HTML) 10 Page - Texas Instruments |
|
|
10 / 56 page  TPS2482 TPS2483 SLUSAW1 A – DECEMBER 2012 – REVISED MARCH 2013 www.ti.com where TJ(max) is the maximum desired transient junction temperature of the pass-MOSFET and TS(max) is its maximum case temperature just prior to a power-limiting event (such as a start or restart). RθJC(max) is the transient junction-to-case thermal resistance of the pass-MOSFET corresponding to the event interval. VPROG is used in conjunction with VDS to compute the (scaled) drain current, ID_ALLOWED, by the constant power- limit engine. ID_ALLOWED is compared by the gate amplifier to the actual ID and used to generate a gate drive. If ID < ID_ALLOWED, the amplifier turns the gate of the pass-MOSFET full on because there is no overload condition; otherwise GATE is regulated to maintain the ID = ID_ALLOWED relationship. A capacitor may be tied from PROG to ground to alter the natural constant power inrush current shape. If properly designed, the effect is to cause the leading step of current in Figure 30 to look like a ramp. PROG is internally pulled to ground whenever EN, POR2, or UVLO are not satisfied, or the TPS2482 is latched off. This feature serves to discharge any capacitance connected to the pin. Do not apply voltages greater than 4 V to PROG. If the constant power limit is not used, PROG should be tied to VREF through a 47-k Ω resistor. SCL: This pin is the clock input for the serial-bus interface. SDA: This pin is the data input for the serial-bus interface. SENSE: Monitors the input voltage at the drain of the pass-MOSFET, and the downstream side of RS providing the constant power limit engine with feedback of both the pass-MOSFET current (ID) and voltage (VDS). Voltage is determined by the difference between SENSE and OUT, while the current analog is the difference between VCC and SENSE. The constant power engine uses VDS to compute the allowed ID and is clamped to 50 mV, acting like a traditional current limit at low VDS. The maximum current limit is set by the following equation: (3) Design the connections to SENSE to minimize RS voltage sensing errors. Don't drive SENSE to a large voltage difference from VCC because there is a non-linear internal impedance between them. The current limit function can be disabled by connecting SENSE to VCC. TIMER: An integrating capacitor, CT, connected to the TIMER pin provides a timing function that controls the allowable fault-time for both versions and the retry interval for the TPS2483. The timer charges at 25 μA whenever the TPS2482 and TPS2483 are in power limit or current limit and discharges at 2.5 μA otherwise. The charge-to-discharge current ratio is constant with temperature even though there is a positive temperature coefficient to both. If TIMER reaches 4 V, the TPS2482 pulls GATE to ground, latches off, and discharges CT. The TPS2483 pulls GATE to ground and attempts a restart (re-enable GATE) after a timing sequence consisting of discharging CT down to 1 V followed by 15 more charge and discharge cycles. The TPS2482 can be reset by either cycling the EN pin or the UVLO (e.g. power cycling). TIMER discharges when EN is low or UVLO or the internal POR2 (power-on reset) are active. The TIMER pin should be tied to ground if this feature is not used. The general equation for fault retry time as a function of CT and retry-application information is found in Applications Using the Retry Feature (TPS2483). VCC: Power supply input for the hotswap section, which provides three functions: 1. biasing power to the integrated circuit, 2. input to the hotswap section power-on reset (POR2) and under voltage lockout (UVLO) functions, and 3. voltage sense at one terminal of RS for the pass-MOSFET current measurement. The voltage must exceed the POR2 threshold (about 6 V for approximately 400 µs) and the internal UVLO turn- on threshold (about 8.4 V) before normal operation (driving the GATE output) may begin. Connections to VCC should be designed to minimize RS voltage sensing errors and to maximize the effect of C1 and D1; place C1 at RS rather than at the device pin to eliminate transient sensing errors. GATE, PROG, PG, and TIMER are held low when either UVLO or POR2 are active. VINM: This pin is Kelvin connected to the negative (load) side of the current sensing resistor. VINP: This pin is Kelvin connected to the positive (source) side of the current sensing resistor. VS: Power supply input for the monitoring section power-on reset (POR1), control logic, ADC, and serial-bus interface. Typically between 2.7 V and 5.5 V. 10 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS2482 TPS2483 |
Similar Part No. - TPS2483PWR |
|
Similar Description - TPS2483PWR |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
