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TPS3421EGDRYR Datasheet(PDF) 3 Page - Texas Instruments

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Part # TPS3421EGDRYR
Description  Low-Power, Push-Button Controllers with Configurable Delay
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TPS3421EGDRYR Datasheet(HTML) 3 Page - Texas Instruments

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TPS3420
TPS3421
TPS3422
www.ti.com
SBVS211A – AUGUST 2012 – REVISED MARCH 2013
ELECTRICAL CHARACTERISTICS
All specifications are over the operating temperature range of –40°C < TJ < +125°C and 1.6 V ≤ VCC ≤ 6.5 V, unless otherwise
noted. Typical values are at TJ = +25°C and VCC = 3.3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCC
Input supply range
1.6
6.5
V
VCC = 3.3 V
250
nA
TPS3421,
VCC = 6.5 V, –40°C < TJ < +85°C
1
µA
TPS3422
VCC = 6.5 V
3.3
µA
Supply current
(standby)
VCC = 3.3 V
350
nA
ICC
TPS3420
VCC = 6.5 V, –40°C < TJ < +85°C
1.2
µA
VCC = 6.5 V
3.4
µA
TPS3420,
PB1, PB2 = 0 V, VCC = 6.5 V
6
12
µA
Supply current
TPS3421
(active timer)(1)
TPS3422
PB1, PB2 = 0 V, VCC = 6.5 V
106
136
µA
TPS3421,
PB1, PB2
0.7 VCC
V
High-level input
TPS3422
VIH
voltage
TPS3420
PB1, PB2
0.85
V
TPS3421,
PB1, PB2
0
0.3 VCC
V
Low-level input
TPS3422
VIL
voltage
TPS3420
PB1, PB2
0
0.3
V
PB1 internal pull-up resistance
RPB1
65
k
Ω
(TPS3422)
TPS3420
PB1, PB2 = 0 V or VCC
–50
50
nA
Input current
TPS3421
IPB
(PB1, PB2)
TPS3422
PB1, PB2 = VCC
-50
50
nA
VCC ≥ 4.5 V, ISINK = 8 mA
0.4
V
VOL
Low-level output voltage
VCC ≥ 3.3 V, ISINK = 5 mA
0.3
V
VCC ≥ 1.6 V, ISINK = 3 mA
0.3
V
Ilkg(OD)
Open-drain output leakage current
High impedance, V RST = 6.5 V
–0.35
0.35
µA
(1)
Includes current through pull-up resistor between input pin (PB1) and supply pin (VCC) for TPS3422.
TIMING REQUIREMENTS
All specifications are over the operating temperature range of –40°C < TJ < +125°C and 1.6 V ≤ VCC ≤ 6.5 V, unless otherwise
noted. Typical values are at TJ = +25°C and VCC = 3.3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
–20%
20%
TPS3420D: TS = GND
6
7.5
9
s
ttimer
Push button timer(1)
TPS3420D: TS = VCC
10
12.5
15
s
TPS3421Ey, TPS3422Ey: TS = GND
6
7.5
9
s
TPS3421Ey, TPS3422Ey: TS = VCC
0
s
–20%
20%
TPS3421xC
64
80
96
ms
trst
Reset pulse duration
TPS3421xG
320
400
480
ms
TPS3422xG
320
400
480
ms
Detection delay (from input to
150
µs
tdd
For 0-s ttimer condition
RST)(2)
Start-up time(2)
VCC rising
300
µs
(1)
For devices with a 0-second delay while TS = VCC, this option is only for factory testing and is not intended for normal operation. In
normal operation, the TS pin should be tied to GND.
(2)
For devices with a 0-second delay when TS = VCC, reset asserts in tdd time when both PB inputs go low in this configuration. During
start up, if the PB inputs are low, reset asserts after a start-up time delay. This value is specified by design.
Copyright © 2012–2013, Texas Instruments Incorporated
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