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ADS1014 Datasheet(PDF) 3 Page - Texas Instruments |
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ADS1014 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 38 page ADS1118 www.ti.com SBAS457C – OCTOBER 2010 – REVISED FEBRUARY 2013 ELECTRICAL CHARACTERISTICS Maximum and minimum specifications are at TA = –40°C to +125°C, unless otherwise noted. Typical values are at TA = +25°C. All specifications are at VDD = 3.3 V, data rate = 8 SPS, and full-scale (FS) = ±2.048 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT Full-scale input voltage range(1) VIN = (AINP) – (AINN) See Table 2 Analog input voltage AINP or AINN to GND GND VDD V Differential input impedance See Table 1 FS = ±6.144 V(1) 8 M Ω FS = ±4.096 V(1), ±2.048 V 6 M Ω Common-mode input impedance FS = ±1.024 V 3 M Ω FS = ±0.512V, ±0.256 V 100 M Ω SYSTEM PERFORMANCE Resolution No missing codes 16 Bits Data rate (DR) 8, 16, 32, 64, 128, 250, 475, 860 SPS Data rate variation All data rates –10 10 % Output noise See Typical Characteristics Integral nonlinearity DR = 8 SPS, FS = ±2.048 V(2) 1 LSB FS = ±2.048 V, differential inputs ±0.1 ±2 LSB Offset error FS = ±2.048 V, single-ended inputs ±0.25 LSB Offset drift FS = ±2.048 V 0.002 LSB/°C Offset power-supply rejection FS = ±2.048 V, with dc supply variation 0.2 LSB/V Gain error(3) FS = ±2.048 V at TA = +25°C 0.01 0.15 % FS = ±0.256 V 7 ppm/°C Gain drift(3)(4) FS = ±2.048 V 5 40 ppm/°C FS = ±6.144 V(1) 5 ppm/°C Gain power-supply rejection 10 ppm/V PGA gain match(3) Match between any two PGA gains 0.01 0.1 % Gain match Match between any two inputs 0.01 0.1 % Offset match Match between any two inputs 0.6 LSB At dc and FS = ±0.256 V 105 dB At dc and FS = ±2.048 V 100 dB Common-mode rejection At dc and FS = ±6.144 V(1) 90 dB fCM = 50 Hz, DR = 860 SPS 105 dB fCM = 60 Hz, DR = 860 SPS 105 dB TEMPERATURE SENSOR Temperature sensor range –40 +125 °C Temperature sensor resolution 0.03125 °C/LSB TA = 0°C to +70°C 0.2 ±0.5 °C Temperature sensor accuracy TA = –40°C to +125°C 0.4 ±1 °C vs supply 0.03125 ±0.25 °C/V (1) This parameter expresses the full-scale range of the ADC scaling. In no event should more than VDD + 0.3 V or 5.5 V (whichever is smaller) be applied to this device. (2) Best-fit INL; covers 99% of full-scale. (3) Includes all errors from onboard PGA and reference. (4) Not production tested; ensured by characterization. Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: ADS1118 |
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